Hi David, > My one other concern is developers using the builtins for applications on > embedded PowerPC processors. lwsync will not order accesses to device > memory space, AFAICT. I do not know if developers would rely on GCC builtins > in that context and assume it implements the correct semantics. Otherwise, > I agree that the memory barrier operations probably can use lwsync.
Thats a good point, but I think embedded driver writers need to create their own synchronisation macros (like Linux and Xorg do). The current gcc builtins only solve some of the issues for drivers and I worry it will give a false confidence if we say they can be used for IO. A few places they will trip up on PowerPC: - eieio required to enforce ordering between non cacheable loads and stores. - eieio doesn't order cacheable and non cacheable storage accesses. To get it right they are going to need IO macros etc. Anton
