Hi, everyone: The address mode in my my RISC chip is like (BaseReg) + 8bit offset, or (BaseReg) + indexReg. And there a 16 general register from R0 to R15 which can be used as Base register or Index Regster.
So you can see that if the frame space is larger than 255, there will be a problem. For a single Load/Store Operation, there should be an additional insn to force the immediate into index register. But this will cause some redundancy code, especially assessing some adjacent area. Like the following code(this is the assemble code generated by my cc1): MOVI #1084 -L ;; Load a immediate to R0 register ADD R5 R0 R14 ;; R14 is regarded as frame pointer STOREH R4 (R5) #0 -PRI ;;load a half word from memory at (R5 + 0). R4 = (R5 + 0) MOVI #1086 -L ADD R4 R0 R14 STOREH R5 (R4) #0 -PRI MOVI #1088 -L ADD R5 R0 R14 STOREH R4 (R5) #0 -PRI You can see the offset loaded three times. But they abut. It can be optimized. I read a paper named ”Optimal Stack Slot Assignment in GCC”. There is an option to enable the stack reorganization. But I didn’t find it in Internal Document. (The SH machine seems to use this method, how do I trigger it?) So I need your guys give me some advices. Thank you very much. _______________________________________________ Best Regards Daniel Tian Mavrix Technology, Inc. Address：200 Zhangheng Road, #3501, Building 3, Zhangjiang Hi-tech Park, Shanghai, P.R.China (201204) Tel:86(21)51095958 - 8125 Fax:86(21)50277658 email：daniel.t...@mavrixtech.com.cn www.mavrixtech.com
