Jean-Marc Saffroy <jean-marc.saff...@joguin.com> writes:
> On 01/28/2011 06:44 PM, Ian Lance Taylor wrote:
>> Jean-Marc Saffroy <jean-marc.saff...@joguin.com> writes:
>>
>>> error: insn does not satisfy its constraints:
>>> (insn 1424 1423 141 (set (reg:DI 2 r2)
>>> (plus:DI (reg:DI 2 r2)
>>> (const_int 40 [0x28])))
>>> /home/jmsaffroy/cygnus/src/newlib/libc/time/strptime.c:165 24 {adddi3}
>>> (expr_list:REG_EQUIV (plus:DI (reg/f:DI 70 a6)
>>> (const_int 40 [0x28]))
>>> (nil)))
>>
>> You should find out what is creating this insn. Is it being created by
>> reload, or is it being created by some pass that runs after reload?
>
> With gcc -da, I see that it appears in dump .195r.ira, so that's reload,
> right?
Right.
>> It is likely that you need to make adddi3 a define_expand which tests
>> reload_in_progress and reload_completed. If those are the case, you
>> will need to explicitly convert
>> (set (reg:DI DREG1) (plus:DI (reg:DI DREG2) (const_int N)))
>> into
>> (set (reg:DI DREG1) (const_int N))
>> (set (reg:DI DREG1) (plus:DI (reg:DI DREG1) (REG:DI DREG2)))
>>
>
> Ah, but here it happens that DREG1 and DREG2 (r2 and a6 above) are
> different types of registers, and I can't add them directly.
The insn you showed is adding a constant to a DREG. There is no
addition of a DREG and an AREG, and I would not expect reload to
generate any such addition either. Are you looking at a different insn?
Don't get confused by the REG_EQUIV note, it's irrelevant here.
Ian
