Hello,
On a vector processor we can do a bswapsi with two instructions, by first
rotating half-words (16 bits) by 8 and then rotating full words by 16.
However, this means expanding:
(set (match_operand:SI 0 "register_operand" "")
(bswap:SI (match_operand:SI 1 "register_operand" "")))
to:
(set (match_dup:V2HI 0)
(rotate:V2HI (match_dup:V2HI 1)
(const_int 8)))
(set (match_dup:SI 0)
(rotate:SI (match_dup:SI 0)
(const_int 16)))
This is obviously not correct, because match_dup cannot set the mode. The point
I am trying to make is that I can't find a good way to deal with the mode
changes. I don't think GCC is too happy if I change the modes of the same
operand from one instruction to the other right? The only other way is to emit
paradoxical subregs. So something along these lines:
(set (subreg:V2HI (match_dup 0) 0)
(rotate:V2HI (subreg:V2HI (match_dup 1) 0)
(const_int 8)))
(set (match_dup 0)
(rotate:SI (match_dup 0)
(const_int 16)))
Is there a better way to handle a situation like this?
Cheers,
Paulo Matos
