https://gcc.gnu.org/g:dd594aab7fb1416b7e06df36ebfe536729df3068
commit r15-441-gdd594aab7fb1416b7e06df36ebfe536729df3068
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue May 14 00:16:36 2024 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 52 +++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cp/ChangeLog | 33 +++++++++++++++++++++++++++++++
gcc/po/ChangeLog | 6 ++++++
gcc/testsuite/ChangeLog | 40 +++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 22 +++++++++++++++++++++
6 files changed, 154 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5d57c861fb62..3aa0ff003fda 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,55 @@
+2024-05-13 Jeff Law <j...@ventanamicro.com>
+
+ * config/riscv/bitmanip.md: Add new splitter for AND with
+ a constant that masks off bits 32..63 and needs synthesis.
+
+2024-05-13 Sergei Lewis <sle...@rivosinc.com>
+
+ * config/riscv/riscv.md (movmem<mode>): Use
riscv_vector::expand_block_move,
+ if and only if we know the entire operation can be performed using one
vector
+ load followed by one vector store
+
+2024-05-13 Vladimir N. Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/115013
+ * lra-constraints.cc (process_alt_operands): Update all_used_nregs
+ only for winreg. Ignore reg starvation for small reg classes.
+
+2024-05-13 Pan Li <pan2...@intel.com>
+
+ PR target/114988
+ * config/riscv/riscv-vector-builtins.cc
+ (validate_instance_type_required_extensions): New func impl to
+ validate the intrinisc func type ops.
+ (expand_builtin): Validate instance type before expand.
+
+2024-05-13 Jeff Law <j...@ventanamicro.com>
+
+ * config/riscv/bitmanip.md (bextseqzdisi): New patterns.
+ * config/riscv/.riscv.cc.swo: New file.
+ * config/riscv/j: New file.
+
+2024-05-13 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/60276
+ * tree-vect-stmts.cc (vectorizable_load): Do not exempt
+ pure_slp grouped loads from the STMT_VINFO_MIN_NEG_DIST
+ restriction.
+
+2024-05-13 Richard Biener <rguent...@suse.de>
+
+ * tree-vect-slp.cc (vect_analyze_slp_instance): Remove
+ slp_inst_kind_reduc_group handling.
+ (vect_analyze_slp): Add the meat here.
+
+2024-05-13 Jakub Jelinek <ja...@redhat.com>
+
+ PR middle-end/113982
+ * tree-ssa-math-opts.cc (arith_overflow_check_p): Also return 1
+ for RSHIFT_EXPR by precision of maxval if shift result is only
+ used in a cast or comparison against zero.
+ (match_arith_overflow): Handle the RSHIFT_EXPR use case.
+
2024-05-13 YunQiang Su <s...@debian.org>
Revert:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 70e23263719f..9c258c501dbf 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240513
+20240514
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index a9f54d8f14ab..ae7b60c51174 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,36 @@
+2024-05-13 Patrick Palka <ppa...@redhat.com>
+
+ * constraint.cc (norm_info::norm_info): Take a bool instead of
+ tsubst_flags_t.
+ (norm_info::generate_diagnostics): Turn this predicate function
+ into a bool data member.
+ (normalize_logical_operation): Adjust after norm_info changes.
+ (normalize_concept_check): Likewise.
+ (normalize_atom): Likewise.
+ (get_normalized_constraints_from_info): Likewise.
+ (normalize_concept_definition): Likewise.
+ (normalize_constraint_expression): Likewise.
+ (normalize_placeholder_type_constraints): Likewise.
+ (satisfy_nondeclaration_constraints): Likewise.
+ * cp-tree.h (enum tsubst_flags): Remove tf_norm.
+
+2024-05-13 Ken Matsui <kmat...@gcc.gnu.org>
+
+ PR c++/115061
+ * semantics.cc (finish_trait_expr): Use rank instead of
+ __array_rank.
+
+2024-05-13 Patrick Palka <ppa...@redhat.com>
+
+ PR c++/114974
+ PR c++/114901
+ PR c++/114903
+ * pt.cc (maybe_aggr_guide): Fix obtaining TYPE_FIELDS in
+ the paren init case. Hoist out partial substitution logic
+ to apply to the paren init case as well.
+ (alias_ctad_tweaks): Substitute outer template arguments into
+ a guide's constraints.
+
2024-05-11 Ken Matsui <kmat...@gcc.gnu.org>
* cp-trait.def: Define __is_nothrow_invocable.
diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog
index 8a4f18ed68f0..2b1fc6e7b193 100644
--- a/gcc/po/ChangeLog
+++ b/gcc/po/ChangeLog
@@ -1,3 +1,9 @@
+2024-05-13 Joseph Myers <josmy...@redhat.com>
+
+ * be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
+ ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
+ zh_TW.po: Update.
+
2024-05-02 Joseph Myers <josmy...@redhat.com>
* gcc.pot: Regenerate.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 62655d5399dd..b1a2b72f3267 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,43 @@
+2024-05-13 Jeff Law <j...@ventanamicro.com>
+
+ * gcc.target/riscv/zba_zbs_and-1.c: New test.
+
+2024-05-13 Sergei Lewis <sle...@rivosinc.com>
+
+ PR target/112109
+ * gcc.target/riscv/rvv/base/movmem-1.c: New test
+
+2024-05-13 Pan Li <pan2...@intel.com>
+
+ PR target/114988
+ * gcc.target/riscv/rvv/base/pr114988-1.c: New test.
+ * gcc.target/riscv/rvv/base/pr114988-2.c: New test.
+
+2024-05-13 Patrick Palka <ppa...@redhat.com>
+
+ PR c++/114974
+ PR c++/114901
+ PR c++/114903
+ * g++.dg/cpp2a/class-deduction-aggr14.C: New test.
+ * g++.dg/cpp2a/class-deduction-alias20.C: New test.
+ * g++.dg/cpp2a/class-deduction-alias21.C: New test.
+
+2024-05-13 Jeff Law <j...@ventanamicro.com>
+
+ * gcc.target/riscv/zbs-bext-2.c: New test.
+ * gcc.target/riscv/zbs-bext.c: Fix one of the possible expectes
sequences.
+
+2024-05-13 Rainer Orth <r...@cebitec.uni-bielefeld.de>
+
+ PR c++/98529
+ * g++.dg/modules/stdio-1_a.H (scan-lang-dump): Allow for
+ ::std::printf.
+
+2024-05-13 Jakub Jelinek <ja...@redhat.com>
+
+ PR middle-end/113982
+ * gcc.dg/pr113982.c: New test.
+
2024-05-13 Paul Thomas <pa...@gcc.gnu.org>
PR fortran/113363
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 1fb87edfb3bd..418adceb66b4 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,25 @@
+2024-05-13 Matthias Kretz <m.kr...@gsi.de>
+
+ PR libstdc++/114958
+ * include/experimental/bits/simd.h (__as_vector): Return scalar
+ simd as one-element vector. Return vector from single-vector
+ fixed_size simd.
+ (__vec_shuffle): New.
+ (__extract_part): Adjust return type signature.
+ (split): Use __extract_part for any split into non-fixed_size
+ simds.
+ (concat): If the return type stores a single vector, use
+ __vec_shuffle (which calls __builtin_shufflevector) to produce
+ the return value.
+ * include/experimental/bits/simd_builtin.h
+ (__shift_elements_right): Removed.
+ (__extract_part): Return single elements directly. Use
+ __vec_shuffle (which calls __builtin_shufflevector) to for all
+ non-trivial cases.
+ * include/experimental/bits/simd_fixed_size.h (__extract_part):
+ Return single elements directly.
+ * testsuite/experimental/simd/pr114958.cc: New test.
+
2024-05-07 Jonathan Wakely <jwak...@redhat.com>
* include/bits/unicode.h (_Unicode_view::_M_read_utf8): Ensure
