https://gcc.gnu.org/g:7b2ffa6b43dbbb6a66397002c8d51ce79ddb9c9a
commit r15-11457-g7b2ffa6b43dbbb6a66397002c8d51ce79ddb9c9a Author: GCC Administrator <[email protected]> Date: Wed Aug 5 00:20:52 2026 +0000 Daily bump. Diff: --- gcc/ChangeLog | 11 +++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 10 ++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a14065a5176..fb16a680e11d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2026-08-04 Jin Ma <[email protected]> + + Backported from master: + 2026-07-16 Jin Ma <[email protected]> + + * config/riscv/riscv.cc (riscv_regno_to_class): Map t1 to + JALR_REGS. + * config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Document + the SIBCALL_REGS restriction. + (REG_CLASS_CONTENTS): Remove t1 from SIBCALL_REGS. + 2026-08-03 Hu, Lin1 <[email protected]> PR target/126581 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 509e118b6738..abc8f80bb9fa 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20260804 +20260805 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0f29dd480e0f..e6d9ae8bb29a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2026-08-04 Jin Ma <[email protected]> + + Backported from master: + 2026-07-16 Jin Ma <[email protected]> + + * g++.target/riscv/pr97682.C: Accept registers in SIBCALL_REGS. + * gcc.target/riscv/rvv/base/sibcall-scalable-frame-indirect.c: + New test. + * gcc.target/riscv/rvv/base/sibcall-scalable-frame-weak.c: New test. + 2026-08-03 Hu, Lin1 <[email protected]> PR target/126581
