https://gcc.gnu.org/g:1f9dc1fbeb067d19f7c4302318cc4d5df63fcdeb
commit r17-5314-g1f9dc1fbeb067d19f7c4302318cc4d5df63fcdeb Author: GCC Administrator <[email protected]> Date: Mon Oct 19 00:16:34 2026 +0000 Daily bump. Diff: --- ChangeLog | 5 ++ gcc/ChangeLog | 140 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/algol68/ChangeLog | 9 ++++ gcc/testsuite/ChangeLog | 50 +++++++++++++++++ libgfortran/ChangeLog | 15 ++++++ libstdc++-v3/ChangeLog | 5 ++ 7 files changed, 225 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index 2eac840250db..eb7035b2be3b 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2026-10-18 Igor Shevlyakov <[email protected]> + + * MAINTAINERS: Regenerate. + * MAINTAINERS.yml: Add record for myself. + 2026-10-16 Pietro Monteiro <[email protected]> PR bootstrap/103459 diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8cf7c637ed37..08417dfa292b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,143 @@ +2026-10-18 Roger Sayle <[email protected]> + + * optabs.def (aop_optab): Change from OPTAB_DC to OPTAB_C. + * rtl.def (AOP): Remove/revert AOP rtx code. + +2026-10-18 Roger Sayle <[email protected]> + + * fold-const.cc (tree_expr_maybe_signaling_nan_p): The result of + an arithmetic operation or math function can't be a signaling NaN. + +2026-10-18 Takayuki 'January June' Suwa <[email protected]> + + * config/xtensa/xtensa.cc (xtensa_is_insn_L32R_p): + Modify it to return false if the given insn corresponds to + CONST.[SD]. + +2026-10-18 Max Filippov <[email protected]> + + * config/xtensa/constraints.md (Gc): Update comment and drop _S from + TARGET_HARD_FLOAT_CONST. + * config/xtensa/xtensa-protos.h (xtensa_expand_conditional_move): + Change second argument type to machine_mode. + * config/xtensa/xtensa.cc (xtensa_class_max_nregs): New + function. + (TARGET_CLASS_MAX_NREGS): Define new macro. + (gen_float_relational): Generate DF mode comparisons in addition + to SF. + (xtensa_expand_conditional_branch): Change TARGET_HARD_FLOAT to + TARGET_FLOAT32 under the E_SFmode case. Add + gen_float_relational() call under the E_DFmode case. + (gen_conditional_move): Handle DFmode case. + (xtensa_expand_conditional_move): Change second argument type to + machine_mode. Change if/else check for floating point/integer + move to a switch for integer/single precision/double precision + floating point move. + (xtensa_copy_incoming_a7): Separate E_DImode and E_DFmode code + and handle E_DFmode case by emitting gen_movdf_internal. + (xtensa_emit_movcc): Generate conditional moves for DFmode. + Use .s suffix, because .d is not handled by the assembler and + both .s and .d instructions have the same encoding. + (xtensa_option_override): Initialize xtensa_hard_regno_mode_ok_p + for DFmode. + (print_operand): Add support for 'T' and 'B' codes. Expand 'U', + 'V' and 'G' conditions to cover DFmode. + (xtensa_rtx_costs): Change TARGET_HARD_FLOAT to TARGET_FLOAT32. + Define costs for FP operations on DF mode values when + TARGET_FLOAT64 is on. + (xtensa_legitimate_constant_p): Cover DF mode case. Return true + for 0 and FP constants supported by const.d instruction when + TARGET_FLOAT64 is on. + (xtensa_zero_call_used_regs): Change TARGET_HARD_FLOAT to + TARGET_FLOAT32. Handle double precision FPU registers by + emitting gen_movdf_concat. + (FPreg_neg_scaled_simm12b): Change TARGET_HARD_FLOAT to + TARGET_FLOAT32. + * config/xtensa/xtensa.h (TARGET_HARD_FLOAT): Change to to be on + when either single precision or double precision hardware FP + support is present. + (TARGET_FLOAT32): Define to 1 when single precision FPU is + available, 0 otherwise. + (TARGET_FLOAT64): Define to 1 when double precision FPU is + available, 0 otherwise. + (TARGET_HARD_FLOAT_DIV): Rename to TARGET_FLOAT32_DIV. + (TARGET_HARD_FLOAT_RECIP): Rename to TARGET_FLOAT32_RECIP. + (TARGET_HARD_FLOAT_SQRT): Rename to TARGET_FLOAT32_SQRT. + (TARGET_HARD_FLOAT_RSQRT): Rename to TARGET_FLOAT32_RSQRT. + (TARGET_FLOAT64_DIV, TARGET_FLOAT64_RECIP, TARGET_FLOAT64_SQRT) + (TARGET_FLOAT64_RSQRT): Define similarly to TARGET_FLOAT32_*, + but for double precision FPU. + (TARGET_HARD_FLOAT_CONST_S): Rename to TARGET_HARD_FLOAT_CONST + and include 64-bit instruction variants into the condition. + (UNITS_PER_FPREG): Define as 8 when 64-bit FPU is available, 4 + otherwise. + * config/xtensa/xtensa.md (UNSPEC_CONCAT): New unspec constant. + (SDF): New mode iterator for SF and DF. + (sd, sdf_mode_bits): New mode attributes. + (addsf3, subsf3, mulsf3, fmasf4, fnmasf4, abssf2, negsf2) + (fix<s_fix>_truncsfsi2, *fix<s_fix>_truncsfsi2_2x) + (*fix<s_fix>_truncsfsi2_scaled, float<s_float>sisf2) + (*float<s_float>sisf2_scaled, l<m_round>sfsi2) + (*l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled, *lsip, *ssip) + (cbranchsf4, cstoresf4, movsfcc, movsfcc_internal0) + (movsfcc_internal1, s<code>_sf): Extend support to DF mode using + SDF iterator and corresponding attributes. + (extendsfdf2, truncdfsf2, movdf_concat): New patterns. + (movdf): Don't force second argument to a memory const if it + satisfies the Gc constraint. + (movdf_internal): Add instructions for arguments matching the f + constraint. Don't do the split if either argument is in the + hard FP register. + +2026-10-18 Jeff Law <[email protected]> + + * config/riscv/bitmanip.md (*<bitmanip_optab>3_mask_si): Fix mode + for masked shift count. + (*<bitmanip_optab>si3_sext_mask): Likewise. + +2026-10-18 Uros Bizjak <[email protected]> + + PR target/127900 + * config/i386/i386.md (*bmi2_umul<mode>3_highpart): Mark + operand 1 as commutative. + (<s>mul<mode>3_highpart): Split into... + (umul<mode>3_highpart): ... a define_insn_and_split with a BMI2 + alternative and ... + (smul<mode>3_highpart): ... a define_insn. + (*bmi2_umulsi3_highpart_zext): New pattern. + (*<s>mulsi3_highpart_zext): Split into... + (*umulsi3_highpart_zext): ... a define_insn_and_split with a BMI2 + alternative and ... + (*smulsi3_highpart_zext): ... a define_insn. + (*<s>muldi3_highpart_1): Split into... + (*umuldi3_highpart_1): ... a define_insn_and_split with a BMI2 + alternative and ... + (*smuldi3_highpart_1): ... a define_insn. Use register_operand + for operand 1 and remove redundant MEM_P condition. + (*<s>mulsi3_highpart_zext): Split into... + (*umulsi3_highpart_1_zext): ... a define_insn_and_split with a + BMI2 alternative and ... + (*smulsi3_highpart_1_zext): ... a define_insn. Use + register_operand for operand 1 and remove redundant MEM_P + condition. + (*<s>mulsi3_highpart_1): Split into... + (*umulsi3_highpart_1): ... a define_insn_and_split with a BMI2 + alternative and ... + (*smulsi3_highpart_1): ... a define_insn. Use register_operand + for operand 1 and remove redundant MEM_P condition. + +2026-10-18 Uros Bizjak <[email protected]> + + * config/i386/i386.md (*umul<mode><dwi>3_1): Change to + define_insn_and_split. Merge in the define_split that + converts mul to the mulx pattern. Remove redundant + !(MEM_P (operands[1]) && MEM_P (operands[2])) condition. + Do not assign operands[5] in the split, it has no matching + match_dup. + (*mul<mode><dwi>3_1<nf_name>): Remove redundant + !(MEM_P (operands[1]) && MEM_P (operands[2])) condition. + (*<u>mulqihi3_1<nf_name>): Ditto. + 2026-10-17 Sam James <[email protected]> PR bootstrap/112422 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 21af1df43854..1e7995319f27 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20261018 +20261019 diff --git a/gcc/algol68/ChangeLog b/gcc/algol68/ChangeLog index e14ed75a1e86..ef29265b356d 100644 --- a/gcc/algol68/ChangeLog +++ b/gcc/algol68/ChangeLog @@ -1,3 +1,12 @@ +2026-10-18 Jose E. Marchesi <[email protected]> + + PR algol68/127977 + * a68-low.cc (a68_low_assignation): Compare types using + TYPE_CANONICAL. + * a68-low-moids.cc (lower_proc_mode): Do not + SET_TYPE_STRUCTURAL_EQUALITY. + (lower_union_mode): Likewise. + 2026-10-17 Jose E. Marchesi <[email protected]> * a68-lang.cc (a68_build_a68_type_nodes): Define fixed sized modes diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 49057abe9630..75057e0fe50c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,53 @@ +2026-10-18 Roger Sayle <[email protected]> + + * gcc.dg/fold-signaling-nan-1.c: New test case. + * gcc.dg/fold-signaling-nan-2.c: Likewise. + +2026-10-18 Max Filippov <[email protected]> + + * gcc.target/xtensa/constsynthV2_O2_costs0.c: Adjust + scan-assembler-times count for the hard_float target. + * gcc.target/xtensa/elim_callee_saved.c: Likewise. + * gcc.target/xtensa/double-conv.c: New test. + * gcc.target/xtensa/float-conv.c: New test. + +2026-10-18 John David Anglin <[email protected]> + + * g++.dg/opt/mem-notrap-load-builtin.C: Disable scan-rtl-dump for + 64-bit PA-RISC targets because address splitting separates the + 'this' pointer attribute from the memory expression during expand. + +2026-10-18 John David Anglin <[email protected]> + + * g++.dg/modules/clone-4_b.C: Update scan-assembler pattern to + match either C2 or C4 constructor symbols to fix test failure + on hppa64-hp-hpux11.11 when using the GNU assembler. + +2026-10-18 Uros Bizjak <[email protected]> + + PR target/127900 + * gcc.target/i386/pr127900.c: New test. + +2026-10-18 John David Anglin <[email protected]> + + * c-c++-common/analyzer/omp-parallel-for-1.c: Add additional + option "--param=analyzer-max-svalue-depth=20". + +2026-10-18 John David Anglin <[email protected]> + + * g++.dg/modules/src-loc-1_a.H: Adjust regexp. + * g++.dg/modules/src-loc-1_c.C: Likewise. + +2026-10-18 Jerry DeLisle <[email protected]> + + PR libfortran/127738 + * gfortran.dg/coarray/form_team_ids_1.f90: New test. + +2026-10-18 Jose E. Marchesi <[email protected]> + + PR algol68/127977 + * algol68/compile/pr127977.a68: New test. + 2026-10-17 Jerry DeLisle <[email protected]> * gfortran.dg/coarray_collectives_6.f90: Expect the address of diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog index cefb60a0a63a..a065618b6c02 100644 --- a/libgfortran/ChangeLog +++ b/libgfortran/ChangeLog @@ -1,3 +1,18 @@ +2026-10-18 Jerry DeLisle <[email protected]> + + PR libfortran/127738 + * caf/shmem.c (new_team_id): New function. + (_gfortran_caf_form_team): Use it. Count the FORM TEAM statements + of the current team. + (_gfortran_caf_change_team): Derive the coarray ids from the team's + id. + * caf/shmem/supervisor.c (ensure_shmem_initialization): Initialize + the id of the initial team and the next team id. + * caf/shmem/supervisor.h (struct supervisor): Add next_team_id. + * caf/shmem/teams_mgmt.h (struct caf_shmem_team): Add teams_formed. + (struct shmem_image_info): Replace lastmemid by id. Add new_teams + and new_teams_gen. + 2026-10-17 Sam James <[email protected]> * configure: Regenerate. diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index ce24b35b0f1b..bf535afb26dc 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,8 @@ +2026-10-18 Iain Sandoe <[email protected]> + + * testsuite/lib/libstdc++.exp: Remove STATIC_LIBCXXFLAGS, it is + no longer needed. + 2026-10-16 Pietro Monteiro <[email protected]> * Makefile.in: Regenerate.
