Evan Lavelle wrote:
> Icarus 0.8.3 seems to have problems with a literal expression in a
> conditional statement:
>
> module test;
> initial
> main;
> task main;
> begin
> if(2)
> $write("taken 'if' branch\n");
> else
> $write("taken 'else' branch\n");
> end
> endtask
> endmodule
>
> This (machine-generated) code takes the else branch, and not the if
> branch. iverilog seems to be checking just the bottom bit of the
> conditional; 'if(3)' works Ok.
Verilog has some weird rules for what is considered for boolean
versus vectors, but I do think this is a bug. Icarus Verilog notes
that the condition expression is constant and throws away the dead
code, so this is handled at compile time not run time. It looks
like exactly what you say, and seems fixable. Please file this as
a bug report for me? knudge it's priority a bit because it is
quietly generating the wrong result, a far more serious issue then
the not-so-quiet crash.
> This code segfaults on compilation:
>
> module test;
> initial
> main;
> task main;
> begin
> if(1)
> ;
> end
> endtask
> endmodule
This is clearly also a bug, but a separate bug. Thanks.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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