On 2/19/07, David Baird <[EMAIL PROTECTED]> wrote:
> This is only useful for out-of-order intialisation, so it's not relevant > here anyway. I kinda like it, even if everything is initialized in order :-)
Being able to name your ports, parameters, or fields is always a great boost for readability. In Verilog, I always connect ports by name when I am instantiating a module with more than a handful of ports. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Favorite book: The Design of Everyday Things, Donald A. Norman, ISBN 0-465-06710-7 _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
