The gap between snapshots has been longer for the last few, because I've been quite busy working on them. Lots of new stuff, lots of bug fixes. Most of the new stuff is partially complete. In particular, Xilinx Virtex2 family support is in the works. I seriously lack a regression test suite for fpga synthesis, so I have no reliable way to report progress there.
Elsewhere, a lot of the bugs that have been reported recently have been fixed by this snapshot. My goal for the 0.8 release is to get Virtex2 synthesis useable, get black box synthesis working in general, and get SWIFT working. Here are the snapshot files: <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20030308.tar.gz> <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20030308.txt>
Release Notes for Snapshot 20030329 A whole bunch of new functionality has been added to the PLI1 support and the cadpli module. Many more Cadence compatible PLI1 modules should now work with Icarus Verilog runtime. Also, a bunch of 2001 updates have been applied. Internally, parameter constants are made available to code generators. This in turn allows VPI access to them. This helps with certain pli modules that really insist on parameter arguments instead of arbitrary constants. Slightly improved support for return values of system functions. This information has been moved to a compiled table. This new format has been used to add a few new system functions that return real values, and $bitstoreal and $itor now work. A few signed arithmetic bugs have been fixed. Also, certain compare expressions now evaluate in constants properly, and have well defined widths. These fixed a variety of expression bugs. synthesis of case statements has been improved to properly allow for default cases. This was causing assertion failures.
Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
