[ Ales here, I'm reposting this since majordomo didn't recognize the e-mail as being subscribed to the geda-dev/geda-user mailinglist. ]
-- Cut here -- Delivery-Date: Mon, 22 Nov 2004 23:35:11 -0500 From: rodrigo benenson <[EMAIL PROTECTED]> but the C generator allow the easy creation of interfaces for the simulations. Actually I consider the direct Confluence->C generation a good thing of Confluence. Having an "all in one" language add points to choice Confluence over other HDL toolkit aviables. rodrigob. On Mon, 22 Nov 2004 23:09:54 -0600, Tom Hawkins <[EMAIL PROTECTED]> wrote: > Stephen Williams wrote: > > Tom Hawkins wrote: > > | I started to define the format for FNF: the future netlist format of > > | Confluence and InFormal. > > | > > | FNF is a flat netlist that retains hierarchical scoping. The netlist is > > | a directed graph of primitive RTL operations, called cells. Some basics: > > | - All cells have 0 or 1 outputs. > > | - All cells operate on bit vectors. > > | > > | The syntax definition is located here: > > | > > | http://www.confluent.org/wiki/doku.php?id=fnf:main > > | > > | (Steve, hopefully this aligns with Icarus synthesis, when you move it > > | from bits to vectors.) > > > > It does indeed appear to jive well enough. You will eventually be > > a need for data type declarations, as I expect nets to eventually > > be typed. > > Hopefully nothing more complex than signed/unsigned. Actually, why not > convert all signed operations to unsigned ops for the internals? This > would make the primitive set a bit smaller -- my approach with Confluence. > > > > > | Shortly I will release an FNF generator for Icarus, followed by a > > | Verilog, VHDL, C, and NuSMV writer. > > > > I think a generator for 0.8 will not be wasted, even though the 0.9 > > branch is changing the ivl_target API. The concepts will be similar > > enough. What I see in the FNF page you have so far is compatible > > with both. > > > > This really starts to get interesting when there are translaters from > > FNF to vvp. I'm starting to imagine mixed language Verilog/schematics > > simulation, post synthesis simulation, et al. > > Yes. I would prefer if Confluence users simulate with Icarus, rather > than having to maintain a redundant C model generator. Then they could > take advantage of full VCD visability (currently lacking in CF). > > Any plans for C model extraction with Icarus 0.9? > > -Tom > > > -- > > Steve Williams "The woods are lovely, dark and deep. > > steve at icarus.com But I have promises to keep, > > http://www.icarus.com and lines to code before I sleep, > > http://www.picturel.com And lines to code before I sleep." > > --------------------------------------------------------------------- > To unsubscribe, e-mail: [EMAIL PROTECTED] > For additional commands, e-mail: [EMAIL PROTECTED] > >
