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I'm doing some reworking on the Icarus Verilog scheduler, and ran
into a pair of tests in the ivtest suite that seem to contradict
each other. Therefore, I would like people with access to the tools
to try out the attached two sample programs on a variety of tools.
The attached programs try to test how the non-blocking assignment
assignments are scheduled through a netlist. I believe that sched2
should pass and nblkpush should fail, but it would be best to take
a vote amongst all the existing tools.
For the record, sched2 passes and nblkpush fails Icarus Verilog 0.8.
Thanks,
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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//
// Copyright (c) 2001 Stephan Boettcher <[EMAIL PROTECTED]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Validates Non-blocking assignment propagation
// $Id: nblkpush.v,v 1.1 2001/10/27 03:04:44 sib4 Exp $
module test;
reg a, b, c, d;
wire ab = a & b;
wire abc = ab | c;
wire abcd = abc & d;
initial
begin
a = 0;
b = 1;
c = 0;
d = 1;
#1;
a = 1;
if (abcd === 1)
begin
$display("PASSED");
$finish;
end
$display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd);
#1;
if (abcd === 1)
$display("abcd value changed late");
else
$display("abcd value still wrong");
end
endmodule
/*
* Copyright (c) 2002 Stephen Williams ([EMAIL PROTECTED])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg a;
reg b;
wire q = a & b;
initial begin
a = 1;
b = 0;
#1;
if (q !== 0) begin
$display("FAILED -- q did not start out right: %b", q);
$finish;
end
b = 1;
if (q !== 0) begin
// Since b takes the new value with a blocking assignment,
// it is up to the & gate to schedule the q change, and not
// actually push the change through.
$display("FAILED -- q changed too soon? %b", q);
$finish;
end
if (b !== 1) begin
$display("FAILED -- b value did not stick: %b", b);
$finish;
end
// The #0 delay lets the scheduler execute the change to the
// q value, so that we can read the correct value out.
#0 if (q !== 1) begin
$display("FAILED -- q did not change when it should: %b", q);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main