I am moving this thread from geda-user to here at geda-dev.
Steve,
Never mind the second part of my msg below. That test case had an embedded case statement within the first case statement:
SA: //outer case
case (in) // synopsys parallel_case full_case
8'h2a:
begin
next_state = SC ;
next_out = 8'h40 ;
end
8'h1f:
begin
next_state = SB ;
next_out = 8'h20 ;
end
default:
begin
next_state = SA ;
next_out = 8'h04 ;
end
endcase
In this particular bench mark, the input in is defined as 8 bit wide; that is what is casuing the big mux with 8-bit selection to be called for.
Cordially, CN
--Original Message Text---
From: CN
Date: Mon, 08 Aug 2005 10:59:15 -0700
Steve,
Thank you for the suggestion. Yes, you are right, of course. There was a branch for a mux4 synthesis, the rest was going to one place where a mux2 is the only one possible; hence the test was for selection size of 1.
However, I am seeing another problem. I inserted a printf here to show the selection width, and I am getting an incorrect number. For the test case which was working ok, the ivl_lpm_selects(net) came out ==2 correctly. But for the case where the case statement calls for 8 input, the above size is printed out as 8 instead of the expected 3. Any ideas?
Cordially, CN
On Sat, 06 Aug 2005 08:12:46 -0700, Stephen Williams wrote:
CN wrote:
| Hello All,
|
| When I run the attched source prep3.v (it is an old, very small state machine benchmark
test) thru ivl v0.8.1, with -tfpga -parch=virtex
|
| I get something like:
|
| Assertion failed: ivl_lpm_selects(net) == 1, file xilinx.c, line 718
|
| Is there a problem with this test case? Anybody has any suggestions as to how I might
modify ivl to run this? I am willing to do the work, if some guidance can be given.
Thank you for the help!
You are fidding with synthesis here? Hmm..
What seems to be going on here is that the case statement is in an
asynchronous logic block, so it is trying to make a mux. The code
generator for the virtex device only knows how to generate code for
2-input and 4-input NUX devices. Thus when you change the select to
be 2 bits wide instead of 4 bits wide, it's happy.
The solution is to in d-virtex.c add the code needed to generated
nested muxes as needed to handle your 8-input mux.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
