Oops - didn't read far enough down the mailing list...
Here is the output with the corrected file.
Verilog XL
----------
Tool: VERILOG-XL 05.50.002-s Oct 10, 2005 11:03:54
Copyright (c) 1995-2004 Cadence Design Systems, Inc. All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.
Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc. Reproduced with
Permission.
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AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.
Cadence Design Systems, Inc.
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San Jose, California 95134
For technical assistance please contact the Cadence Response Center at
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For more information on Cadence's Verilog-XL product line send email to
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Compiling source file "pr529.v"
Highest level modules:
top
--------- force test failed ---------
force did not affect U2 hierarchy
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool: VERILOG-XL 05.50.002-s Oct 10, 2005 11:03:55
NC Verilog
----------
ncverilog: 05.50-s003: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
Recompiling... reason: file './pr529.v' is newer than expected.
expected: Mon Oct 10 10:53:50 2005
actual: Mon Oct 10 11:00:57 2005
file: pr529.v
module worklib.top:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.top:v <0x652b9caf>
streams: 6, words: 7495
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 3 2
Registers: 11 9
Scalar wires: 4 -
Expanded wires: 4 2
Initial blocks: 5 4
Cont. assignments: 0 3
Writing initial simulation snapshot: worklib.top:v
Loading snapshot worklib.top:v .................... Done
ncsim> source /usr/ldv/tools/inca/files/ncsimrc
ncsim> run
--------- force test failed ---------
force did not affect U2 hierarchy
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Synopsys VCS
------------
Chronologic VCS simulator copyright 1991-2004
Contains Synopsys proprietary information.
Compiler version 7.2; Runtime version 7.2; Oct 10 11:05 2005
--------- force test failed ---------
force did not affect U2 hierarchy
V C S S i m u l a t i o n R e p o r t
Time: 20
CPU Time: 0.010 seconds; Data structure size: 0.0Mb
Mon Oct 10 11:05:10 2005
Stephen
> Delivered-To: [EMAIL PROTECTED]
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> Delivered-To: [email protected]
> Date: Sat, 08 Oct 2005 08:40:17 -0700
> From: Stephen Williams <[EMAIL PROTECTED]>
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Gecko/20050921
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> To: geda-dev <[email protected]>
> Subject: Re: gEDA: Help with sample program
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>
> Dan McMahill wrote:
>
> > ****** force/release to ibus[0] commented; expect bit[0] failure *******
> >
> > --------- force test failed ---------
> > force to single unassigned wire failed
> > force to bit[0] of 2-bit bus failed
>
> Glad I has someone test this for me. That was a sample submitted
> in a bug report. With the output you sent, I was able to correct
> it, I hope. Can you run the attached updated version with the same
> set of tools? It looks correct to me now.
>
>
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
