Friends - On Tue, Jan 24, 2006 at 09:26:15PM -0800, Stephen Williams wrote: > > I was curious when/if you are planning to support constant function calls in > > parameter assignments. > > It hadn't occurred for me to try. I was more motivated to work > on things like generate statements that I perceived to be growing > in use. But now I know there is interest in it, I'll put it in > my head.
generate ... Generate ... GENERATE !!!!
Xilinx XST supports it, and it would make my synthesized-to-FPGA
Verilog code sooo much more maintainable. If I had a clue where
to start, I would have started hacking on it long ago. But this
seems like a very deep part of an implementation, so I decided to
stay out of the way.
- Larry
signature.asc
Description: Digital signature
