Stephen,

I noticed when attempting to instantiate an array of instances that use
explicit port naming that Icarus Verilog does not parse this correctly.
Looks like there is a missing case in the "gate_instance" rule in the
parse.y.

Example of non-working code:

foo bar[3:0] ( .a(a) );

Example of code that Icarus Verilog parses without problems:

foo bar[3:0] ( a );

Later,
Trevor


----- Original Message -----
From: "Stephen Williams" <[EMAIL PROTECTED]>
To: "geda-dev" <geda-dev@seul.org>
Sent: Wednesday, February 15, 2006 12:27 PM
Subject: gEDA: Icarus Verilog Snapshot 20060215


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> This is a fairly small change from the previous snapshot, but fixes
> some bugs that have been reported. Also, it gets past working with
> some of the newer Xilinx unisim models.
>
> <ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20060215.tar.gz>
> <ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20060215.txt>
>
>
> Release Notes for Icarus Verilog Snapshot 20060215
>
> * Part select of memory words should now work according to
>   Verilog-2001. This also led to some cleanup of the handling of types
>   internally, as well as some infrastructure for general arrays.
>
> * Minor fix to parsing of (* *) attributes.
>
> * Fix rounding of reals to integers.
>
> * Clean up some of the vvp engine related to memories. Remove some
>   dead instructions.
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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