I have a lf353 model, below, included in a .sch, also below. I use gnetlist -g spice.sdb xxx.sch.
I get an output that looks OK. Op and dc produce what I expect. However, ac and tran do not. dc v101 -1 +1 .001 plot vout shows linear ramp, gain=10 ac dec 100 1 10meg plot vout shows horizonal line at 0 tran .01ns 5us shows a semi-sine with a down sloping mean from the first peak to the 5th: x0 = 5.65217e-07, y0 = 2.88095 x1 = 4.54348e-06, y1 = 1.7619 dx = 3.97826e-06, dy = -1.11905 dy/dx = -281291 dx/dy = -3.55504e-06 Is this repeatable with ngspice? Have I made an error, or a bad model? Bad circuit? tomdean ======== sch ======================================================== v 20060123 1 C 7000 23000 1 0 0 title-bordered-C.sym C 8700 30800 1 0 0 vsin-1.sym { T 9400 31450 5 10 1 1 0 0 1 refdes=V101 T 9400 31250 5 10 1 1 0 0 1 value=sin 0 1 1meg } C 22000 37800 1 0 0 spice-include-1.sym { T 22500 37900 5 10 1 1 0 0 1 file=lf353_sp3.mod } C 13600 33300 1 90 0 resistor-1.sym { T 13300 33500 5 10 1 1 90 0 1 refdes=R101 T 13700 33800 5 10 1 1 0 0 1 value=1k } C 13600 30000 1 90 0 resistor-1.sym { T 13300 30200 5 10 1 1 90 0 1 refdes=R102 T 13700 30100 5 10 1 1 0 0 1 value=1k } C 13400 28600 1 0 0 gnd-1.sym C 8900 29600 1 0 0 gnd-1.sym C 12400 33900 1 0 0 gnd-1.sym N 8500 36500 9000 36500 4 { T 9100 36500 5 10 1 1 0 0 1 netname=Vm12 } N 10500 36500 11000 36500 4 { T 11100 36500 5 10 1 1 0 0 1 netname=Vp12 } N 15000 32800 16500 32800 4 { T 16000 32900 5 10 1 1 0 0 1 netname=Vout } N 15300 32800 15300 30900 4 N 14000 32600 13500 32600 4 N 13500 32600 13500 30900 4 { T 12900 32400 5 10 1 1 0 0 1 netname=Vfb } N 13500 30900 14400 30900 4 N 13500 30000 13500 28900 4 N 9000 30800 9000 29900 4 N 14000 33000 9000 33000 4 { T 11400 33100 5 10 1 1 0 0 1 netname=Vin } N 9000 33000 9000 32000 4 N 13500 33300 13500 33000 4 N 13500 34200 12500 34200 4 N 14500 33200 14500 34300 4 { T 14600 34200 5 10 1 1 0 0 1 netname=Vp12 } N 14500 32400 14500 31800 4 { T 14600 31900 5 10 1 1 0 0 1 netname=Vm12 } C 14000 32400 1 0 0 lf353-1.sym { T 14200 33300 5 10 1 1 0 0 1 refdes=XU101 T 14800 33100 5 10 1 1 0 0 1 model-name=lf353 } C 14400 30800 1 0 0 resistor-1.sym { T 14600 31100 5 10 1 1 0 0 1 refdes=R103 T 14500 30700 5 10 1 1 270 0 1 value=1k } C 10200 35300 1 0 0 vdc-1.sym { T 10900 35950 5 10 1 1 0 0 1 refdes=V102 T 10900 35750 5 10 1 1 0 0 1 value=DC 12V } C 8200 35300 1 0 0 vdc-1.sym { T 8900 35950 5 10 1 1 0 0 1 refdes=V103 T 8900 35750 5 10 1 1 0 0 1 value=DC -12V } C 10400 35000 1 0 0 gnd-1.sym C 8400 35000 1 0 0 gnd-1.sym T 9700 33100 9 10 1 0 0 0 1 [1] T 13100 32000 9 10 1 0 0 0 1 [2] T 14700 33700 9 10 1 0 0 0 1 [3] T 14100 31900 9 10 1 0 0 0 1 [4] T 15500 32900 9 10 1 0 0 0 1 [5] T 10500 36600 9 10 1 0 0 0 1 [3] T 8600 36700 9 10 1 0 0 0 1 [4] ======== gnetlist output =========================================== * gnetlist -g spice-sdb -o amp.cir amp.sch ********************************************************* * Spice file generated by gnetlist * * spice-sdb version 12.27.2005 by SDB -- * * provides advanced spice netlisting capability. * * Documentation at http://www.brorson.com/gEDA/SPICE/ * ********************************************************* *vvvvvvvv Included SPICE model from lf353_sp3.mod vvvvvvvv *////////////////////////////////////////////////////////////////////// * (C) National Semiconductor, Inc. * Models developed and under copyright by: * National Semiconductor, Inc. =20 *///////////////////////////////////////////////////////////////////// * Legal Notice: This material is intended for free software support. * The file may be copied, and distributed; however, reselling the=20 * material is illegal *//////////////////////////////////////////////////////////////////// * For ordering or technical information on these models, contact: * National Semiconductor's Customer Response Center * 7:00 A.M.--7:00 P.M. U.S. Central Time * (800) 272-9959 * For Applications support, contact the Internet address: * [EMAIL PROTECTED] * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF353 Wide Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT lf353 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA *^Quiescent supply current *EOS 7 1 POLY(1) 16 49 5E-3 1 BOS 7 1 V=5e-3+v(16,49) *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 *F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 B1 9 98 I = 1.0985E7 * (I(VA3)^3) G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS *^^^^^^^^ End of included SPICE model from lf353_sp3.mod ^^^^^^^^ * *============== Begin SPICE netlist of main design ============ R101 Vin 0 1k XU101 Vin Vfb Vp12 Vm12 Vout lf353 .INCLUDE lf353_sp3.mod V103 Vm12 0 DC -12V V102 Vp12 0 DC 12V R103 Vfb Vout 10k R102 0 Vfb 1k V101 Vin 0 sin 0 1 1meg .END ====== lf353_sp3.mod ========================================= *////////////////////////////////////////////////////////////////////// * (C) National Semiconductor, Inc. * Models developed and under copyright by: * National Semiconductor, Inc. =20 *///////////////////////////////////////////////////////////////////// * Legal Notice: This material is intended for free software support. * The file may be copied, and distributed; however, reselling the=20 * material is illegal *//////////////////////////////////////////////////////////////////// * For ordering or technical information on these models, contact: * National Semiconductor's Customer Response Center * 7:00 A.M.--7:00 P.M. U.S. Central Time * (800) 272-9959 * For Applications support, contact the Internet address: * [EMAIL PROTECTED] * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF353 Wide Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT lf353 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA *^Quiescent supply current *EOS 7 1 POLY(1) 16 49 5E-3 1 BOS 7 1 V=5e-3+v(16,49) *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 *F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 B1 9 98 I = 1.0985E7 * (I(VA3)^3) G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user