I applaude your efforts to understand the VHDL back-end. It's too bad it doesn't seem to work easily; I do think that it should "just work".
That being said, I must say that using a schematic capture package to do Verilog or VHDL seems to defeat the purpose. That is, these text-based logic languages have pushed schematic-based logic design aside because they are much easier to deal with once a design has grown beyond a certain (not very large) size. Maybe somebody will contradict me -- which is fine -- but in my experience nobody actually draws logic symbols anymore, except for a few random gates now and then. Rather, real logic designs are captured as Verilog or VHDL in text format, and compiled directly to programming files which are loaded into FPGAs, CPLDs, and the like. At the schematic level one just draws lots of boxes with lots of pins corresponding to the FPGA or CPLD. Therefore, using gschem to draw a logic circuit and then netlist to VHDL isn't a commonly used design flow nowadays. Instead, people just create a textual design using a text editor. Maybe that's why the VHDL netlister hasn't received much attention recently. Stuart On Fri, 16 Feb 2007, Chitlesh GOORAH wrote:
Hello there, I successfully created a vhdl file from http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadder.sch http://tux.u-strasbg.fr/~chit/cours_vhdl/output.net. However, since my schematic includes some and2 and or2, the output.net includes the respective components, but if I compile the vhdl file directly, it will fails since it lacks the and2 and or2 entities. Unfortunately for such a simple schematic. Is there a method to tell gnetlist to include appropriate package name for the and2 and or2 components so that one shouldn't right his own and2 and or2 vhdl file but uses the standard vhdl code? Chitlesh -- http://clunixchit.blogspot.com _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
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