On Sat, Mar 10, 2007 at 04:14:19AM +0000, Peter Clifton wrote: > > In twos complement - for the specific implementation used at least - > which sign extends with the original MSB: > > -2 >> 1 == -1 > -1 >> 1 == -1 > (etc..) > > Clearly this is different from the behaviour for +ve numbers, hence he > discrepency I noted.
Verilog won't sign-extend with >>, you'd want to use >>>. If you are expecting arithmetic right shift and getting logical left shift, you'd get totally different results. If you're sure you're getting arithmetic shift, and you don't like the rouding, you will have to do something about it. The easiest thing would be to add in the MSB (1 for -ve) first. So instead of (x >>> 1) you'd have ((x + x[msb]) >>> 1). That will not change the result for positive (msb = 0) but will fix the rounding for negative x. > Perhaps the best way is for me to keep the cordic operating in the > 0<->45 degree angle range, rather than the -45<->45 I've been using so > far. I thought that was required, but I haven't seen the opencores implementation. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user