Thanks for your answer. It's for me the good solution.
regards, Ludovic Mike Jarabek a écrit : > Hi, > > It has been suggested before that you can designate one copper layer for this > purpose, and just use vias instead of a footprint. > > Wherever you want a strap, just draw a copper line. Print the layer > seperately and you have a reference for your wires. > > Doing it this way will allow the DRC to pass and the rats nest will work too. > > > -------------------------------------------------- > Mike Jarabek > FPGA/ASIC Designer, DSP Firmware Designer > http://www.sentex.ca/~mjarabek > -------------------------------------------------- > > -----Original Message----- > From: Ludovic SMADJA <[EMAIL PROTECTED]> > Date: Tue, 15 May 2007 21:25:46 > To:gEDA user mailing list <geda-user@moria.seul.org> > Subject: gEDA-user: howto : strap use in pcb > > Hello, > > I would know how to put straps on my pcb in order to reduce vias. > > Is it possible and how ? > > > > ------------------------------------------------------------------------ > > > > _______________________________________________ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA "Le hasard, c'est Dieu qui se promène incognito" - Albert Einstein HALTE AUX SPAMS : Cet email est signé. Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2&lang=fr_FR#whyEmails Mes coordonnées : Jabber ID : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] Clé PGP : DD76063A sur pgp.mit.edu
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