On 5/18/07, John Griessen <[EMAIL PROTECTED]> wrote:
Svenn Are Bjerkem wrote:
> I had the dream that I could use Signs VHDL environment for Eclipse
> and extend it with VHDL-AMS capabilities to use an open source
> simulator to do real mixed signal.
The Signs tutorial screen shots and words seem like they have FPGA design in
mind,
and it seems like a tidy way to go about it. I wonder if they have considered
the complexity
of "real mixed signal" though? They have no schematic tool yet...
But they are making automatic schematics with geda symbols from vhdl
like you get when you use synopsys. Not without flaws, though, but the
logic is corrent.
The schematic editor must be made. And I think the connection with
schematic capture and HDL editing would be great. I have been looking
at some circuit and graph editing programs like circuitsmith, yEd and
argo-UML to see how it is possible to borrow ideas. I have also
studied electric a bit, but the editing interface is too old
fashioned. That's the nice thing about Eclipse, the infrastructure is
there, the user only need to write plug-ins to create the interface to
the user. And it is stupid not to learn from UML. There is an
initiative in direction SysUML to use existing UML techniques to do
Semiconductor system specifications.
Something like VisualHDL with a connection between analog and digital
through an HDL-AMS netlist as backend would be great. (Al has been
giving good arguments for using VHDL as a data storage format for
electronic circuits.)
I think the real first steps toward that wish of a goal is to help get
verilog-AMS netlisting to work
with available netlist and schematic tools, (voila gnetlist, gschem), then
hooking that into an IDE should be easy for any IDE
worth it's salt.
I can help out with anything as long as I can access it via cvs or svn
and use Eclipse as an editor.
--
Svenn
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