Stephen Williams <[EMAIL PROTECTED]> writes: >> One difficulty, though: the primitive cells that iverilog emits are >> pretty complex. Is there any way to ask it to break down multipliers >> and adders into stuff no larger than a LUT4?
> The reason it generates at that level is that in some cases it > is the appropriate level. For example, there *are* multipliers > in many modern FPGA primitive sets. It is a whole lot easer for > a code generator to break down a multiplier into gates, then to > merge up gates into a multiplier. Certainly! I was just wondering if I'd be reinventing the wheel by writing code to turn a MULT8 into a bunch of LUT4's. But yes, I'd much rather have MULT8s in the EDIF if the target includes hard multipliers. >> Also, what's the difference between the tgt-edif and tgt-fpga >> directories? > Licensing, mostly. The tgt-edif target source code uses a BSD > style license, whereas the tgt-fpga target (which is currently > a superset) uses the GPL license. Cool; I'll go with tgt-fpga then. Thanks! - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380 _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user