On 7/27/07, John Luciani <[EMAIL PROTECTED]> wrote: > On 7/27/07, armdeveloper <[EMAIL PROTECTED]> wrote: > > On Fri, 2007-07-27 at 14:10 -0400, DJ Delorie wrote: > > > > > .pcb file ? > > > > > > > > You want me to post it ? > > > > > > We can't debug it if we can't reproduce it. > > > > Here is the pcb file... the layout is all messed up at the moment, but > > you'll see what I mean. > > I noticed that the netlist has C2-N and C2-P and the > PCB footprint for C2 has pins "1" and "2". >
Also --- I noticed that the trace from C1-2 hits Q2-1. Did you route with enforce DRC off? Try deleting that trace and correcting the C1 and C2 pin labels. (* jcl *) -- http://www.luciani.org _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user