The PCB DRC tests for 'shrink' compliance by looking for copper areas that stop touching if you draw the individual parts smaller by 'shrink' mil.
My question is: Is this a realistic model of how manufacturing 'shrink' would really affect overlapping copper areas? What first led me to notice this was a via I placed which overlapped a SMT pad. The annulus of the via was solidly over the edge of the pad. The DRC would complain, because in its model, the annulus could shrink AND the pad could shrink and the result would not touch. If I connected them with a wire, I was okay. Rendered as 'ideal' sized pieces, the overlap of the via and pad was wider than the connecting wire, but since the code modelled the pad and via as capable of shrinking independently, the wire was required. So if you imagined a square pad made of up four adjoining squares (easy to do with polygons, in fact), the result is indistinguishable onscreen from one BIG square, but the DRC thinks that due to manufacturing, the sub-squares could shrink individually and quit touching. Is this really true? Or should any copper areas (regardless of how they came to be) shrink only around the outermost periphery? -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user