There is a new snapshot available ... http://www.gnucap.org/devel/gnucap-2008-01-30.tar.gz
Models (optional) have also been updated: http://www.gnucap.org/devel/gnucap-2008-01-30-models-bsim.tar.gz http://www.gnucap.org/devel/gnucap-2008-01-30-models-ngspice17.tar.gz http://www.gnucap.org/devel/gnucap-2008-01-30-models-spice3f5.tar.gz Another optional package contains some tools: http://www.gnucap.org/devel/gnucap-2008-01-30-tools.tar.gz This snapshot provides: 1. Root circuit in Spectre or Verilog format. (in addition to Spice format) 2. Command syntax in spectre format (when lang=spectre). In general, command syntax depends on the language. Language choices are: spice, acs, spectre, verilog. 3. Case sensitivity and units (SI or Spice) normally tracks the language, but can be overridden. As usual, to get started you need only the main package gnucap-2008-01-30.tar.gz . The other "models" packages contain the exact models from the various sources. If you need a jfet, I recommend the one in "spice3f5". If you need a BSIM model, the obvious choice is the "bsim" package, which has all of them. The "ngspice17" package contains a few models not available elsewhere, such as "vbic". If you need others, let me know. Others, such as Josephson junction, are available, but I have not ported them yet. Porting a Spice model usually requires two files, a "Makefile" and a "wrapper.h", and no other changes. _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user