On Feb 4, 2008 6:44 PM, David Griffith <[EMAIL PROTECTED]> wrote: > On Mon, 4 Feb 2008, Stuart Brorson wrote: > > > This created an interesting problem with power/vdd-1.sym which has > > > "net=Vdd:1". These statements are not case-insensitive. > > > > If you are using the vdd-1.sym symbol in your design, then this > > attribute is creating a global net called Vdd, whether you want it or > > not. If you want this, that's fine. If not, then you need to change > > the name of the net to your desired netname, e.g. "net=mynetname:1". > > Right, but there was the bizarre effect of some object containing > net=Vcc:? and net=Vdd:? somewhere, but disappearing when the Vcc and Vdd > symbols were not used. That made me suspect there's a problem in the > interpretation of the symbol files, not in the symbols themselves.
The problem is likely to be symbol files that contain embedded power nets. Unless you are doing a large digital board you may want to use symbols that do not contain embedded power nets. I use symbols without the embedded power nets and then place a separate power symbol. I have a script that removes embedded power nets and creates power symbols. See http://www.luciani.org/geda/util/util-index.html (* jcl *) -- http://www.luciani.org _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user