Dave N6NZ wrote: >but I do urge you to consider the ultimate readability of the result.
I do this all the time -- at least I try. I can see your point. For really big devices division is a good thing. For FPGA it is easy to divide it in banks, power.... I have divided a 64 pin ADC in a similar way, see my page at gedasymbols.org But I am not absolutely sure if such a division make too much sense for 32 pin parts like ADC ADS6125 from TI. Regards Stefan Salewski _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user