Good day! I'm just a NB in Verilog design, sorry if my question is too stupid :)
I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. I became familiar with IV modelling system, but synth restrain my activity - i get strange error with the simplest module: module D (clk, reset, out, in); input clk, reset, in; output out; reg out; always @ (negedge clk) if (reset) out <= 1'b0; else out <= in; endmodule iverilog -tfpga test.v test.v:7: sorry: Forgot to implement NetCondit::synth_sync test.v:6: error: Unable to synthesize synchronous process. 2 error(s) in post-elaboration processing. Where is my mistake? What should i read to understand my problem? Thanks! _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user