>The code was designed for a CPLD, so perhaps there is a difference. In >ISE, with the FPGA I'm putting down buffer symbols which tell it what >kind of IO to use. If you could directly map the "INOUT" port to a pin >on the chip (where "0" or "Z" output states would make sense), that >works intuitively.
>What I couldn't do was take the inout lines, and connect them to the >outside world via an IOBUF. Ahhh... This is where things went wrong. ISE is capable of inferring the IOBUF from the VHDL. The IOBUF is a primitive, that you can't connect to your 'internal' tri state bus. Best to connect the ports from the underlying module directly to 'inout' ports at the top level. I ran into this type of behaviour before when integrating IP blocks from various places, some of them assumed that the synthesis tool added the IOBUF in the netlist, while others did not. We had to edit the toplevels a bit to get them all on the same plan. One thing to watch out for with your I2C interface is that you really should sample the SDA line half way through the bit period, and that you should filter the inputs, as they have really slow rise times. Every I2C block I have seen from vendors have clocked internal logic directly from the SCL line, and this is dangerous. Sample and re-time the line with a high rate clock and sample the SDA line at the right time, with a delay generated by the master clock. In the past I have used a state machine to carry this out. Thanks, -----Original Message----- From: Peter Clifton <[EMAIL PROTECTED]> Date: Fri, 27 Jun 2008 00:02:30 To: gEDA user mailing list<geda-user@moria.seul.org> Subject: Re: gEDA-user: OT: (Vhdl help) On Thu, 2008-06-26 at 15:22 -0700, Ben Jackson wrote: > On Thu, Jun 26, 2008 at 11:07:49PM +0100, Peter Clifton wrote: > > > > This is similar to the code in the Xilinx I2C entity. > > > > When I try to assign from the input port of the IOBUF using similar > > code, I just end up getting this error. > > > > http://www.xilinx.com/support/answers/14264.htm > > Right, FPGAs don't really have internal tri-state (or wired-or) busses. > If you had two I2C modules connected to the same pins, the I/O/T model > allows you to combine them at one output. If the module just took 'SDA' > and did the tri-stating internally then I would expect you to get that > error when you connected another I2C module. Actually, its physical pins on the device I'm wanting to connect it to. The code was designed for a CPLD, so perhaps there is a difference. In ISE, with the FPGA I'm putting down buffer symbols which tell it what kind of IO to use. If you could directly map the "INOUT" port to a pin on the chip (where "0" or "Z" output states would make sense), that works intuitively. What I couldn't do was take the inout lines, and connect them to the outside world via an IOBUF. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
