On Wed, Oct 8, 2008 at 11:40 PM, John Doty <[EMAIL PROTECTED]> wrote: > > On Oct 8, 2008, at 2:25 PM, Stefan Salewski wrote: > >> Am Dienstag, den 07.10.2008, 13:05 -0600 schrieb John Doty: >>> >>> Your problem is that you're trying to hang two names on one net. >>> There is no support for this, and no definition of what should happen >>> if you try. >>> >> >> Seems that direct connection of a power-symbol (net=+3.3V:1) and a >> io-symbol (net=RAM_HIGH:1) gives similar problems, no connection is >> generated >> > > Another case occurs in hierarchy: suppose two pins are directly > connected through the circuit specified by "source=". The higher > level nets on those pins won't be connected. > > But the question is, how should this work? >
Maybe there should be "aliases" for the nets? I don't know how is it handled in other EDA systems... If I connect two nets with different names one gets renamed (message: "Found duplicate net name, renaming [DATA_IN1] to [DATA_OUT2]"). If aliases were available, just an alias should be created. -- Wojtek Zabolotny [EMAIL PROTECTED] _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user