On Fri, 2009-01-16 at 12:30 -0500, DJ Delorie wrote: > > Not digital, but this is similar to a load circuit I built in the lab. > > Yeah, something like that. > > Kudos to email-able schematics :-) > > > The actual circuit ended up with most of RLoad in the emitters of > > the FETs to ensure better balancing. > > Did your FETs have positive or negative thermal coefficients?
Not sure, but the emitter resistors ought to help them share. (Not that they were drawn in the schematic). The FETs were SPP80N03. Charts show threshold voltage drops with increasing temperature, R_DS(on) increases. I'm not sure what the overall effect would look like. The emitter resistors are all 10-25W metal heat-sink mount resistors (not got the rating to hand), mounted on a heat-sink with each transistor next to its power resistor, a common gnd-bus-bar threaded through the power resistors, and a power bus bar soldered to the transistor drains. This was all semi-dead-bug style, as the gate resistors are also supported in space by their leads, one end on the mounted FET. another on a gate-bus bar, terminated on a connector plate mounted one end of the heat sink. I can't quite recall, but I think the final design used more than 4 paralleled channels. The whole thing was supposed to burn up to 600W peak, and was used for programmable load cycling of batteries under test. For low voltage cells I had to bootstrap the battery with a lab power-supply, as the circuit started to have stability problems once it ran out of head-room. The control input in my case was a cheap National Instruments DAQ card analogue output. I did think of designing a switched mode load, but in the end the simplicity of linear won out. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user