I've made a little library of devices with IO pins with pin labels p and n. I get a netlist with pin numbers 1 and 2. I also have model files with same first part as placed devices then a .va extension -- cap-va.va
I'm thinking of changing to p and n pin numbers. Any other suggestions before using with gnucap? How close is this example netlist to loading in gnucap? ---------------------------------- module verilog_io ( GND , C , A ); /* Port directions begin here */ inout GND ; inout C ; inout A ; /* Wires from the design */ wire B ; wire GND ; wire C ; wire A ; /* continuous assignments */ /* Package instantiations */ \cap-va C1 ( .\1 ( B ), .\2 ( GND ) ); \ind-va L1 ( .\2 ( C ), .\1 ( B ) ); \res-va R1 ( .\2 ( B ), .\1 ( A ) ); endmodule ------------------------- John Griessen -- Ecosensory Austin TX _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user