I'm pretty sure this idea is going to work. My design, although large in component count, is really just a bunch of identical blocks repeated many times. For example, there's an input buffer section that's copied 8 times. Each of those buffers has a hierarchical reference designator, say S1/S101/partNum where S1/S101 signifies the hierarchicl block prefix, and partNum is the various parts within the block (like R1, C1, etc.). All the partNum's are the same from block to block, so S2/S101/partNum is the same as S1/ S101/partNum.
So here's the plan: 1. Place and route all the parts of one hierarchical block, for example S1/S101. 2. Select all the parts from S2/S101 and delete them ( I don't think there's a 'delete selected' menu, but 'cut to buffer' should work out). 3. Copy/paste S1/S101. For now, there's going to be 2 copies of S1/S101/partNum. 4. Select the copied section. 5. Save the layout. I noticed that the .pcb file retains the the attribute 'selected' which will help me filter the file. 6. Filter the file, renaming all the 'selected' parts that match 'S1/S101' with 'S2/S101'. That should now give me a perfect copy, routes and all, layer by layer (I think) the perfectly matches my netlist. Assuming it works, I want to say that PCB file format makes stuff like this pretty easy! gene _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
