On Wed, Mar 11, 2009 at 11:12 AM, 温宇杰 <yujie....@celestialsemi.cn> wrote: > > always @(posedge CLK or RESET) begin > if (RESET == 1) begin Q = 0; > end
I don't know much about iverilog but you may want to try this form: always @(posedge CLK or posedge RESET) begin Regards, -r _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
