Josef Wolf wrote: > Hmm, I have the feeling that with the help of this list, I am already > pretty close to the solution: > > - Use pads (instead of vias) on the solder side to represent the holes > - connect them on the solder side with lines > - lock pads+lines > - fiddle eps output to change the color of the solder side > - place parts as usual > - use copper on component side for routing. The routes appear black in > the printout > > Have I missed something?
It sounds like you will have a grey solder side layer, so the pads will only be on one side at all -- routes that the netlister and drc checks use need to be on the same side as the pads. So, if you do not use vias your black to grey change to .ps output can't be for the whole side, that would get the pads, (connected to the routing), and the routing. all would be grey. I think that is ready for some testing. One thing you could do with your template .pcb drawing is include some trace segments of the right lengths to align well as part of a copyable "library" of parts for students to use. That is, if they are going to be doing "layout". So try what DJ mentioned. Test if connectivity is made by overlapping a footprint pad on a via without creating errors or not allowing it. If there is a trouble with that, each component will have to have some trace attached to each pad also and the trace makes the netlist connectivity as usual. vias connect to the other side and allow easy grey postprocessing of .ps "other side" output. John -- Ecosensory Austin TX tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1 _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user