The Verilog target for Icarus Verilog needs attention. If it were it a usable (even compilable) state, it would be of use to you. Is it sits, getting it it working order would be a great summer project for somebody.
Philipp Klaus Krause wrote: > Is it possible to use Icarus to simplify Verilog code? > I would like to use Berkeley VL2MV/VIS and SIS or ABC, however these > tools understand only a very limited subset to verilog. Can Icarus be > used to synthesize Verilog into a simplified Verilog? SIS and ABC seem > to be a good tools for optimization and can do some technology mapping. > > The Verilog subset understood by VL2MV (which I use to convert Verilog > to BLIF, which is used by SIS and ABC) is a bit limited, e.g. no > functions, no multiplication or division. Details can be found in > http://www.zemris.fer.hr/labosi/osstr/doc/vl2mv.pdf > If Icarus could "synthesize" Verilog to a simplified Verilog usable by > VL2MV, this would lead e.g. to an improved open flow for ASIC design. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user