Hi all, an interesting discussion thanks for sharing it with the list. I have done the "star topology" Vcc design as is described here with great results, but only in the correct set of circumstances.
Most of the PCB design I do for work is RF related typically 900MHz to about 5GHz, for consumer cellular smartphone applications. The idea behind that consultant's work is reasonable, if there are lots of mixed signal parts and only some of the Vcc nodes are particularly sensitive. Most bypass caps of large value (say 1uF or even 0.1uF) dont look like capacitors at 3GHz, it is well beyond their self-resonant frequency, and at those frequencies the parasitic inductance of their construction dominates, so they do little to isolate RF noise at that frequency. If you look at the RF S-Parameters of the capacitor at frequencies above the self resonance, they look inductive, not capacitive. Good RF decoupling standard practice is to use a smaller cap (e.g. 20pF in parallel with some larger ones such as 1000pF _and_ 0.1uF or larger as needed) to get a good broad band capacitive reactance across frequency). The smaller value is of course placed closest to the IC and the next largest value near that, all of them are still near the load point at the IC. The use of a VCC trace back to a central point (which would also have a parallel network of similar decoupling capacitors provides a series inductance to RF energy, and then the shunt decoupling caps at the common point, further shunt the signal. This gives you a shunt C, series L, shunt C from the IC to the central Vcc point, and another series L and shunt C to any other Vcc load point in the circuit (assuming the same practice is applied on the second Vcc load point). This can provide a lot of isolation between Vcc nodes. As Mr. Paddock quite correctly pointed out, this will raise inductance, and for the RF frequencies that might cause EMI or degrade an RF receivers performance, in this one specific case, raising the inductance is a good thing once we have some shunt C. This can be helpful in the case where one Vcc pin on an IC is especially sensitive, such as the low noise amplifier input, and another might be noisy (the digital section of a mixed signal IC). If both Vcc nodes were tied to the same plane any RF energy entering that plane could easily couple to the other section. However if you are doing a very large digital design with limited / no RF section, this can be impractical in the extreme, and if any of the Vcc nodes draw a lot of current, the IR drops can be an issue. Also if there are lots of high current switching transients (e.g. a large microprocessor, having a stiff supply with a plane approach is probably a better bet. One other caution, is if the length of Vcc traces approaches 1/2 a wavelength of the highest frequency in use in your design. This length can be calculated from the dielectric constant of the PCB substrate (for fiberglass that is about 7 cm / GHz for half a wavelength). If the Vcc traces exceed this length, then you should put a high frequency (small value) decoupling cap at that distance to prevent the Vcc lines from resonating and causing very odd behavior. I have seen and used a hybrid approach with a Vcc plane for the digital section of a board, and a significant amount of decoupling, including a ferrite bead followed by more decoupling, to create a common Vcc point for just the RF section of a mixed signal board. Note I don't wish to imply that the consultant's recommendation applies to your design or not, obviously there are trade-offs, I am just trying to illustrate the logic behind the recommendation so you can find what works best for you. Regards, --Neil Hendin. Sr. RF Design Engineer. Palm Inc. Sunnyvale, CA ----- Original Message ---- From: "geda-user-requ...@moria.seul.org" <geda-user-requ...@moria.seul.org> To: geda-user@moria.seul.org Sent: Mon, October 19, 2009 8:41:35 AM Subject: geda-user Digest, Vol 41, Issue 31 Send geda-user mailing list submissions to geda-user@moria.seul.org To subscribe or unsubscribe via the World Wide Web, visit http://www.seul.org/cgi-bin/mailman/listinfo/geda-user or, via email, send a message with subject or body 'help' to geda-user-requ...@moria.seul.org You can reach the person managing the list at geda-user-ow...@moria.seul.org When replying, please edit your Subject line so it is more specific than "Re: Contents of geda-user digest..." Today's Topics: 1. Eliminate separate Vcc planes? (Bob Paddock) 2. Re: net= attributes, symbols and schematics (John Luciani) 3. Re: net= attributes, symbols and schematics (John Luciani) 4. Re: Eliminate separate Vcc planes? (Andy Fierman) 5. Re: Eliminate separate Vcc planes? (Gene Heskett) 6. Re: Eliminate separate Vcc planes? (John Griessen) 7. Re: PCB burn in spec? (Ellec, Chris) 8. Re: Eliminate separate Vcc planes? (andrew whyte) 9. Re: Eliminate separate Vcc planes? (andrew whyte) ---------------------------------------------------------------------- Message: 1 Date: Mon, 19 Oct 2009 08:35:33 -0400 From: Bob Paddock <graceindustr...@gmail.com> Subject: gEDA-user: Eliminate separate Vcc planes? To: gEDA user mailing list <geda-user@moria.seul.org> Message-ID: <a3aee9a50910190535gc14d760t7e6d55f830cc6...@mail.gmail.com> Content-Type: text/plain; charset=windows-1252 Boss just sent around something he got from a consultant on doing "proper" EMI design (which I've been doing for years already, I thought until consultant came up with this): "Eliminate separate Vcc planes. This ancient practice is long overdue for an overhaul. Years ago, the leaded capacitors were not able to provide a good enough short at VHF and above, so the reasoning was that the parallel plates of Vcc and ground made a good UHF capacitor. The problem with this is twofold: it takes away one or more ground planes, and more importantly doesn?t allow the designer to control where the noise current goes. Noise follows the path of least impedance, which may be anywhere on the PCB after you punch holes in the Vcc plane for vias and to route traces that have no other room to go. The best way to control noise is to use a separate trace for Vcc, and apply series and shunt elements to control the noise currents." There is no attribution as to were that advice comes from. The frequencies in question are 400 MHz to 3 GHz. To me running Vcc traces all over the board is the surest way to raise inductance etc., and seems wrong to me. Want to know what you thought of this consultants advice? Doesn't cover what happens in multi-rail systems either. ------------------------------ Message: 2 Date: Mon, 19 Oct 2009 08:52:55 -0400 From: John Luciani <jluci...@gmail.com> Subject: Re: gEDA-user: net= attributes, symbols and schematics To: gEDA user mailing list <geda-user@moria.seul.org> Cc: geda-u...@seul.org Message-ID: <608bfe540910190552g3abdf08dte2ca1b0504f98...@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1 On Thu, Oct 15, 2009 at 2:54 PM, Stephen Williams <st...@icarus.com> wrote: > > I was thinking about multi-part symbols, actually. It would be > kool to draw a symbol for all the business pins and another symbol > for the power pins. Then I could have a sheet just for power/gnd. This is what I would do. I would also make these footprints heavy so that the footprint attribute is always found. > But I wondered about netlisting and refdes support. Bummer that > renumbering doesn't preserve relationships. I believe my refdes_update script does. I can't remember if I thought it was a good idea and implemented it or thought it was a good idea and would add it later ;) Try it on a backup copy of your schematic. (* jcl *) -- You can't create open hardware with closed EDA tools. twitter: http://twitter.com/jluciani blog: http://www.luciani.org ------------------------------ Message: 3 Date: Mon, 19 Oct 2009 08:52:55 -0400 From: John Luciani <jluci...@gmail.com> Subject: Re: gEDA-user: net= attributes, symbols and schematics To: gEDA user mailing list <geda-user@moria.seul.org> Cc: geda-u...@seul.org Message-ID: <608bfe540910190552g3abdf08dte2ca1b0504f98...@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1 On Thu, Oct 15, 2009 at 2:54 PM, Stephen Williams <st...@icarus.com> wrote: > > I was thinking about multi-part symbols, actually. It would be > kool to draw a symbol for all the business pins and another symbol > for the power pins. Then I could have a sheet just for power/gnd. This is what I would do. I would also make these footprints heavy so that the footprint attribute is always found. > But I wondered about netlisting and refdes support. Bummer that > renumbering doesn't preserve relationships. I believe my refdes_update script does. I can't remember if I thought it was a good idea and implemented it or thought it was a good idea and would add it later ;) Try it on a backup copy of your schematic. (* jcl *) -- You can't create open hardware with closed EDA tools. twitter: http://twitter.com/jluciani blog: http://www.luciani.org ------------------------------ Message: 4 Date: Mon, 19 Oct 2009 15:18:25 +0100 From: Andy Fierman <andyfier...@signality.co.uk> Subject: Re: gEDA-user: Eliminate separate Vcc planes? To: gEDA user mailing list <geda-user@moria.seul.org> Message-ID: <7b4b1a5b0910190718u42bab660v8d3703cb363de...@mail.gmail.com> Content-Type: text/plain; charset=windows-1252 So your consultant thinks it's a bad idea to have a Vcc plane because it takes up space that you could use for additional ground planes and that you might need to run traces ... ... and then urges you to run power traces where? In the - now empty - Vcc plane layer? Or in the same layer as your already (according to your consultant) full signal layers, leaving you a whole layer to put a shiny new ground plane into? Hmmm. Suppose you have a 6 layer PCB with one continuous ground pane and one continuous Vcc plane (dream on ...). It's not ideal but not everyone wants to pay the extra for 8 layers. layer 1 = signal (set up for 50R trace impedance w.r.t. ground plane) : small spacing : layer 2 = ground plane : small spacing : layer 3 = signal (set up for 50R trace impedance w.r.t. ground plane) : big spacing! (to minimise Xtalk between layers 3 to 4) : layer 4 = signal (set up for 50R trace impedance w.r.t. Vcc plane) : small spacing : layer 5 = power plane : small spacing (set up for 50R trace impedance w.r.t. Vcc plane) : layer 6 = signal All the return currents for signals on layers 4 & 6 run over the power plane until they get decoupled to layer 2 ground plane. Not ideal but if the Vcc plane is properly decoupled to the ground plane with good ceramic decouplers adjacent to all signal sources and destinations (some of which may be dedicated and some shared Vcc decouplers anyway) then that is OK. (Note that with 6 layers you cannot gain much from the capacitance between the ground and Vcc planes because you have two signal layers sandwiched between them and so must keep those traces far enough apart to keep the crosstalk between them negligible.) And then you remove the plane from layer 5 ...... The return currents for layers 4 & 6 now run in layer 2 ground but the trace impedances have skyrocketed because their image plane is now many times further away. Crosstalk between signals on layer 4 and on layer 6 is now huge because it is proportional to 1/(1+(D/H)^2) where D is the spacing between the adjacent traces on a layer and H is the height above the image (ground) plane. Crosstalk between signals on layer 6, 4 and 3 is now also huge because they are no longer screened or effectively separated from each other. Oh and you might be putting signals on layer 5 too? The reduction of the total copper available to supply current to the devices is slashed because it's only through individual traces. Voltage drops increase due to the DC resistive losses. Dynamic voltage drops increase due to the residual switching currents that the discrete decoupling cannot remove being drawn through the increased inductance and skin effect resistance of the supply traces rather than a low inductance Vcc plane. If you replace the Vcc plane with a ground plane then that would be nearly ideal (assuming you properly via the two ground planes together to keep the return path currents close to any signal vias that transfer signals on traces referred to one ground plane to traces referred to the other). But if you could do that then wouldn't you have done it to start with? As for the assumption that you put signal traces into a Vcc plane layer. There are cases where you might have to but if you are so worried about running out of routing space and can afford to replace the power plane with a ground plane then you should not be putting traces into that Vcc plane in the first place. As you say, if your running stuff around in the GHz region then this is just a nonsense. Even the very best ceramic caps still look inductive much above 1GHz so they are still far from the ideal parts you'd like to be able to sprinkle like fairy dust over all your noisy parts and for you return paths. As you mention; if you have a multi-rail system then you either have a power plane layer that looks like the classic "Patchwork fields of England" with lots of plane breaks (in which case you may have a problem waiting to catch you out) or you already have a PCB with extra layers in it to accommodate all these planes. I can't see this advice catching on in many of those well known whizzy processor motherboards. Sorry if this seems like a bit of a rant or if you feel I have offended your Grandmothers legendary egg sucking abilities but ... Hopefully you can gently persuade your boss that this is not quite what the very expensive consultant meant to say. And I'll just go and calm down now. Cheers, Andy. www.signality.co.uk 2009/10/19 Bob Paddock <graceindustr...@gmail.com>: > Boss just sent around something he got from a consultant on > doing "proper" EMI design (which I've been doing for years already, > I thought until consultant came up with this): > > "Eliminate separate Vcc planes. > This ancient practice is long overdue for an overhaul. ?Years ago, the > leaded capacitors were not able to provide a good enough short at VHF > and above, so the reasoning was that the parallel plates of Vcc and > ground made a good UHF capacitor. ? The problem with this is twofold: > it takes away one or more ground planes, and more importantly doesn?t > allow the designer to control where the noise current goes. ? Noise > follows the path of least impedance, which may be anywhere on the PCB > after you punch holes in the Vcc plane for vias and to route traces > that have no other room to go. ?The best way to control noise is to > use a separate trace for Vcc, and apply series and shunt elements to > control the noise currents." > > There is no attribution as to were that advice comes from. ?The > frequencies in question are 400 MHz to 3 GHz. > To me running Vcc traces all over the board is the surest way to raise > inductance etc., and seems wrong to me. > > Want to know what you thought of this consultants advice? > > Doesn't cover what happens in multi-rail systems either. > > > _______________________________________________ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ------------------------------ Message: 5 Date: Mon, 19 Oct 2009 10:50:49 -0400 From: Gene Heskett <gene.hesk...@verizon.net> Subject: Re: gEDA-user: Eliminate separate Vcc planes? To: gEDA user mailing list <geda-user@moria.seul.org> Message-ID: <200910191050.49558.gene.hesk...@verizon.net> Content-Type: Text/Plain; charset=windows-1252 On Monday 19 October 2009, Bob Paddock wrote: >Boss just sent around something he got from a consultant on >doing "proper" EMI design (which I've been doing for years already, >I thought until consultant came up with this): > >"Eliminate separate Vcc planes. What's he/she smoking, it must be great stuff and I want a sample. >This ancient practice is long overdue for an overhaul. Years ago, the >leaded capacitors were not able to provide a good enough short at VHF >and above, so the reasoning was that the parallel plates of Vcc and >ground made a good UHF capacitor. The problem with this is twofold: >it takes away one or more ground planes, and more importantly doesn?t >allow the designer to control where the noise current goes. Noise >follows the path of least impedance, which may be anywhere on the PCB >after you punch holes in the Vcc plane for vias and to route traces >that have no other room to go. The best way to control noise is to >use a separate trace for Vcc, and apply series and shunt elements to >control the noise currents." > >There is no attribution as to were that advice comes from. And as a C.E.T. with 60 years of electronics experience, troubleshooting to the part level, I sure as heck would not want my name attached to such advice. >The >frequencies in question are 400 MHz to 3 GHz. >To me running Vcc traces all over the board is the surest way to raise >inductance etc., and seems wrong to me. It is. But it is sometimes helpful to make those layers a bit like a star topology to help steer the noise properly and keep it from going willy-nilly anyplace it wants to go. >Want to know what you thought of this consultants advice? Rubbish. Whats worse is that your boss probably _paid_ for that advice. >Doesn't cover what happens in multi-rail systems either. -- Cheers, Gene "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) The NRA is offering FREE Associate memberships to anyone who wants them. <https://www.nrahq.org/nrabonus/accept-membership.asp> The law will never make men free; it is men who have got to make the law free. -- Henry David Thoreau ------------------------------ Message: 6 Date: Mon, 19 Oct 2009 10:07:00 -0500 From: John Griessen <j...@ecosensory.com> Subject: Re: gEDA-user: Eliminate separate Vcc planes? To: gEDA user mailing list <geda-user@moria.seul.org> Message-ID: <4adc8094.3050...@ecosensory.com> Content-Type: text/plain; charset=windows-1252; format=flowed Andy Fierman wrote: > So your consultant thinks it's a bad idea to have a Vcc plane because > it takes up space . . . > Hopefully you can gently persuade your boss that this is not quite > what the very expensive consultant meant to say. So, are there no conditions where leaving out a VCC plane makes sense? He might not have meant to compare to 3GHz motherboards. If he meant to deal with RF transceivers as special case zones, and the rest of the circuits operate below some clock speed like 600MHz, I can imagine a stack up like: for a four layer board... signal + VCC ============= GND1 ============= signal2 ============= GND2 ============= signal3 + VCC2 or for a six layer board signal1 ============= signal2 ============= GND1 ============= signal3 ============= GND2 ============= signal4 ============= signal5 for slower analog + VCC on 4,5 transmission lines on 3 switching + VCC2 on 1,2 Zones of power plane around mixed signal chips seem good sense -- they'd act as pure capacitance and a place to hook bypass caps of various levels of pure capacitance without hogging all the area. And traces can be thick as you like -- 1 cm wide...or so... Now if we could just specify blind vias easily with pcb... John ------------------------------ Message: 7 Date: Mon, 19 Oct 2009 11:33:39 -0400 From: "Ellec, Chris" <chris.el...@brooksinstrument.com> Subject: Re: gEDA-user: PCB burn in spec? To: <geda-user@moria.seul.org> Message-ID: <d8c37abfbf987942b75f600b8b4570fae52...@ushat-exm01.brooksinstrument.com> Content-Type: text/plain; charset="us-ascii" We want to do powered burn in of populated boards, to catch bad solders and early component failures. I'm thinking 0-65C. Chris. > Message: 5 > Date: Thu, 15 Oct 2009 19:50:13 -0400 > From: Bob Paddock <bob.padd...@gmail.com> > Subject: Re: gEDA-user: PCB burn in spec? > To: gEDA user mailing list <geda-user@moria.seul.org> > Message-ID: > <bf689bbe0910151650w59047f44t54896d7fb6f01...@mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > On Wed, Oct 14, 2009 at 3:05 PM, Ellec, Chris > <chris.el...@brooksinstrument.com> wrote: > > > > Can somebody recommends burn in spec. for PCB such as time vs. > > temperature? Is there a mil spec for that? I could only > find mil-spec > > for burning in individual IC, not PCB (mil-std-883 for example). > > Unpopulated boards? > > Populated boards with or without power while being burned in? > > What is the actual goal you want by doing burn in? > > What we did for populated, unpowered, boards was 65'C for 24 hours, > then into a -20'F freezer for 24 hours, for four cycles of > that, when we > wanted to thermal cycle solder joints. Don't know if there was spec, > it was what someone came up with at the CM I worked. > > > ------------------------------ Message: 8 Date: Mon, 19 Oct 2009 16:38:53 +0100 From: andrew whyte <ajwh...@gmail.com> Subject: Re: gEDA-user: Eliminate separate Vcc planes? To: gEDA user mailing list <geda-user@moria.seul.org> Message-ID: <2db97fa10910190838o52cac264mfba37da47d63f...@mail.gmail.com> Content-Type: text/plain; charset=UTF-8 I can't suggest much that hasn't been already stated. A good reference book "Printed Circuit board design techniques for EMC compliance" (ISBN0-7803-5376-5) it has interesting advice about different layre stackups and the effects on inductance and decoupling (now 9 years old but still in print) It doesn't suggest removing the Vcc layres for RF design. I think that I would still use Vcc planes and decouple heavily (nobody ever got the sack for adding more decoupling ;-) ), but perhaps it is worth questioning this... At 3GHz can you assume that your Vcc and GND are shorted any more? Probably not, but I suppose that depends on your power topology and the inductance of the Vcc line. Everyone seems to agree that the amount of capacitance that comes from the planes is minimal and that noise can be distributed by the power planes. I can see that your consultant didn't voice himself in the most politically sensitive manner. I've never seen it advised that Vcc planes be completely removed, but, since they don't really add much decoupling capacitance, you might imagine times when routing thick tracks as differential pairs with the ground plane on signal layres would make the design less likely to have ground loops or mistakenly violate moating. Perhaps you'd be best to ask him why he see's Vcc planes as categorically wrong? I'd be interested to hear back what he says ;-) ------------------------------ Message: 9 Date: Mon, 19 Oct 2009 16:41:32 +0100 From: andrew whyte <ajwh...@gmail.com> Subject: Re: gEDA-user: Eliminate separate Vcc planes? To: gEDA user mailing list <geda-user@moria.seul.org> Message-ID: <2db97fa10910190841n100e8fbfub5f4f62f2e986...@mail.gmail.com> Content-Type: text/plain; charset=UTF-8 for clarification: > ...?you might imagine times when routing thick > tracks as differential pairs with the ground plane on signal layres [instead > of a Vcc plane]. > would make the design less likely to have ground loops or mistakenly > mistakenly >violate moating. ------------------------------ _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user End of geda-user Digest, Vol 41, Issue 31 ***************************************** _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user