Anthony Shanks wrote: > Hi all, > > 3. Right now, I am running gnetlist -g PCB on my schematics to > generate the pcb netlist file. The problem is I have multiple > schematics that I am generating a netlist from and I am manually > appending the refdes to indicate which schematic the netlist comes > from so all my refdes will be unqiue. (for example, instead of U1, it > will be U1.A1). Has anybody developed some kind of script or flow to > solve this problem? I would like to get away from doing this manually > eventually.
What you can do is create a top schematic with symbols created for the A1 A2 etc. schematics and attach attribs for doing hierarchic names to flat netlist. On each symbol for a sub schematic put attrib source=A1.sch or source=A2.sch as needed. then your netlist output will have names like: SENVDDB S6/R4-1 S6/C4-1 S5/R4-1 S5/C4-1 S4/R4-1 S4/C4-1 S3/R4-1 S3/C4-1 S2/R4-1 S2/C4-1 S1/R4-1 S1/C4-1 Q5-3 U4-5 Q2-3 SENVDDA S6/R2-1 S6/C2-2 S5/R2-1 S5/C2-2 S4/R2-1 S4/C2-2 S3/R2-1 S3/C2-2 S2/R2-1 S2/C2-2 S1/R2-1 S1/C2-2 Q4-3 U4-3 Q1-3 SENSIGS1R2 S1/C3-2 S1/R3-1 U2-13 where a wire named SENVDDB connects to 6 places with the same component name, but prefixed with the sub schematic name. For making repeated layout zones, I made a script version from one of John Luciani's. See http://www.gedasymbols.org/user/john_griessen/tools/pcb-hier-cells John -- Ecosensory Austin TX _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user