On Wed, Aug 4, 2010 at 2:02 PM, Stephen Williams <st...@icarus.com> wrote: > > This looks like a bug in Icarus Verilog, I'm afraid. Since all the > values in your expression have explicit sizes, the bit width need > not have carry space tacked on and the width should be 26bits. > In fact, in your example the bus is particularly nasty because it > causes the enablemask bits to be shifted up a bit in the concatenation! Yes, that is how I ran into it in the first place!
> > I see that you filed a bug report, that's good. I'll probably bump > its priority a notch because in certain situations it is giving an > incorrect result without warning. In the spirit of wanting to give back, I've decided to spend the rest of the day seeing I can track down the source of this bug and to submit a proposed patch. Of course, I am not nearly as familiar with the code as you and Cary are, so don't hope for too much. But I feel I should make a little more contribution than just filing bug reports (as valuable as they are). Wish me luck. And if you have any tips or pointers for where I should start looking, I'd be glad to hear them. (I have already verified that the vvp file thinks it's operating on a 17 bit value instead of a 16 bit value, so I've narrowed it down to not being a VVP problem -- which seems pretty obvious, but I like to eliminate the obvious as quickly as possible so as to not be surprised by it later :-)) --wpd _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user