Hi,
Does any one know about any book that describes how to convert a behavioral code into unoptimized gate level netlist. I know that after an unoptimized gate level netlist is got logic synthesis is applied to get an optimized netlist. I have a book called Algorithms for VLSI Design Automation. It has a chapeter on high level synthesis. But it doesnt explain my above question. I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. Regards, Ronald On 9/5/10, Ronald Mathias <[1]ronnie.math...@gmail.com> wrote: Hi, Thanks a lot. Regards Ronald Mathias On 9/4/10, Philipp Klaus Krause <[2]...@spth.de> wrote: Am 04.09.2010 06:19, schrieb Ronald Mathias: > > > I transform the Verilog code containing behavioral statements into > verilog code that contains only gate level instantiations. This is > passed as input to ABC Logic synthesis tool. Finally the > output generated by ABC is passed to Versatile Place and Route(VPR) > program which generates the bitstream. You don't have to go down to gate level: Simple verilog, (e.g. still allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can the use vis to flatten the resulting blif-mv into blif, which can be read by abc. This is the way I currently do synthesis (for a simulated asic, directly writing the simple verilog vl2mv understands; the resulting gate level verilog is then simulated in Icarus to get timing). Philipp _______________________________________________ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:ronnie.math...@gmail.com 2. mailto:p...@spth.de 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
_______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user