On 12/31/2010 08:02 AM, Stephen Trier wrote:
I was wondering whether there would be a demand for this style of logic symbol in gschem.
Most logic designers now use verilog blocks for such logic and never even make a diagram with visual cues like IEEE symbols have. Since much low level logic is synthesized for chips or FPGAs these days, and there is often a way to probe signals anywhere, the meaning conveyed by control wires as in up, down, clr, is only made more obvious when using probes or verilog testbench code. Making function visually obvious seems to be skipped since just after IEEE symbols were proposed in the 70's. Except for TIs discrete logic parts. John -- Ecosensory Austin TX _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user