I've been trying to use the pcb track optimization tools on a board which I've manually routed. I tried essentially all the options on the Connects | Optimize routed tracks menu. However, I've run into a couple of problems:
1. My board has an LQFP48 footprint rotated 45 degrees. Whenever I try to use the optimization tools, weird stairstep tracks appear on this IC's pads, shorting all of them together. 2. The optimization tools violated the DRC minimum spacing constraints. I removed the LQFP48 IC and instead put some circular “test pad” footprints in place of each of the IC's pads. I was then able to get the optimization tools to sort-of-work. However, the tracks were pulled too close to some other pins and it violated DRC minimum copper spacing. Also, my tracks weren't very nicely pulled and optimized either. Has anyone encountered these problems? What is the status of the pcb track optimization features? Do they perform better for automatically-routed tracks? Are they useful only for very simple layouts? Regards, Colin _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user