On Tue, 15 Jun 2004 09:33:11 +0200, Levente KOVACS <[EMAIL PROTECTED]> wrote: > > On Mon, 14 Jun 2004 17:22:09 -0400 > William Dieter <[EMAIL PROTECTED]> wrote: > > > Is there any way to add clearance for lines in the same layer group as > > polygons, but in different layers? I am using pcb-20040530. > > I think that does not makes so much sence. Imagine, that you have 2 > layer board. You have a line at the top layer, and a ground plane at the > bottom. Why should the botom layer cleard?
That's not what I want to do. I agree that if they layers are physically different, a line should not clear polygons in other layers. However, pcb allows layers to be grouped, so that logically separate traces can be put in different "layers" even though layers in the same group are put into the same physical layer on the board. The reason for grouping layers is to make it easy to distinguish between traces in the same layer (for example, if you have Vcc and GND traces on the same layer as signals.) By default, pcb has three layers "solder", "GNC-sldr", and "Vcc-sldr" that are grouped together in the same physical layer on the board. There are three similarly grouped layers on the component side as well. If a trace in the Vcc-sldr layer overlaps a trace in the GND-sldr layer they will be shorted together in the final design. I am designing a two layer board and the component layer is mostly ground, but I need to use the component layer to route a few signal traces. I could put the signal traces and the ground into the same layer and get the line-clearing effect I want. The layout looks nicer and is easier to understand if the ground is in the GND-comp layer and the signal traces are in the component layer, but pcb doesn't create any clearance around the signal traces. I would have to manually carve out behind all the traces prevent the traces from being shorted to ground. Bill.
