On Friday 07 January 2005 11:38 am, Daniel J Wisehart wrote: > I know that going to a VHDL like structure would be > convenient for one of the tools, but all of the other tools > would have to change. And does it really make sense to have > Verilog inside of a VHDL block?
No matter what standard is chosen all of the tools need to change. The translation between VHDL and Verilog is simple to the extent that the features overlap. Both are growing to accommodate the features of the other, so in time there will be no difference other than syntax. If the only difference is syntax, that is trivial to deal with. We rely on translators now, so adopting a standard like this doesn't really change anything. Just make translators to and from the standard. My preference for VHDL over Verilog is because it has some features that I consider important. If syntax was the only concern, I would prefer Verilog. "Spectre-HDL" is even better, from a syntax viewpoint, but it isn't an official standard.
