1 module test (x);
2 output x;
3 wire b;
4 assign x = b;
5 endmodule$ iverilog -Wall test.v $ # Nothing!
I'm running 0.8.
Thanks!
-Tom
1 module test (x);
2 output x;
3 wire b;
4 assign x = b;
5 endmodule$ iverilog -Wall test.v $ # Nothing!
I'm running 0.8.
Thanks!