On Tue, Nov 01, 2005 at 07:07:05PM -0600, David Hart wrote: > On Tue, 2005-11-01 at 16:52 -0500, Darrell Harmon wrote: > > Though not a GNU project, the JHDL Project is an OpenSource project. > >From their web site at: > > http://www.jhdl.org/overview.html > > there is this short teaser about JHDL: > > Simply put, JHDL is a structurally based Hardware Description > Language (HDL) implemented with JAVA. > > Available appendages to the JHDL circuit model include a set of > tools for debugging, simulating, testing and interfacing to the > circuit, both as it exists in simulation ("in software",) and > while the program is executing on an FPGA ("in hardware.") > > In its current state JHDL includes: > * a library that supports Xilinx 4K, Virtex, and Virtex II > series devices. > > I'd be interested in your assessment of this tool. I haven't used it yet > myself, but it looks to be a great tool for looking into FPGA > technology. > > > > > In the project I am currently working on, I am trying to do most > > of the work in a DSP rather than the FPGA so users can make more > > modifications without having to install non free sofware. > > > > Darrell Harmon > > http://dlharmon.com > -- > David Hart <[EMAIL PROTECTED]> >
It appears that JHDL produces EDIF output which must be converted to a bitstream by Xilinx tools. I believe Icarus Verilog has similar support for some Xilinx parts, and I plan to take a look at that someday. Darrell Harmon http://dlharmon.com
