> it puts T1 & T2 into pcb so the V1 accounts for the missing footprint > error i guess
V1 is likely a SPICE voltage source. This cuts directly to the problem with using SPICE schematics for layout, as discussed here: http://geda.seul.org/dokuwiki/doku.php?id=geda:faq-simulation#why_not_reuse_my_simulation_schematic_for_layout
