[gem5-dev] changeset in gem5: inorder: don't stall after stores

[Korey Sewell]

changeset 9ccf5354e3a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9ccf5354e3a4
description:
        inorder: don't stall after stores
        once a ST is sent off, it's OK to keep processing, however it's a 
little more
        complicated to handle the packet acknowledging the store is completed

diffstat:

 src/cpu/inorder/resources/cache_unit.cc |  10 +++++-----
 src/cpu/inorder/resources/cache_unit.hh |   4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diffs (41 lines):

diff -r 26a0b8a1ecb8 -r 9ccf5354e3a4 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc   Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc   Sun Jun 19 21:43:38 2011 -0400
@@ -240,17 +240,17 @@
     inst->unsetMemAddr();
 
     // Erase from Address List
-    vector<Addr>::iterator vect_it = find(addrList[tid].begin(),
+    std::list<Addr>::iterator list_it = find(addrList[tid].begin(),
                                           addrList[tid].end(),
                                           mem_addr);
-    assert(vect_it != addrList[tid].end() || inst->splitInst);
+    assert(list_it != addrList[tid].end() || inst->splitInst);
 
-    if (vect_it != addrList[tid].end()) {
+    if (list_it != addrList[tid].end()) {
         DPRINTF(AddrDep,
                 "[tid:%i]: [sn:%i] Address %08p removed from dependency "
-                "list\n", inst->readTid(), inst->seqNum, (*vect_it));
+                "list\n", inst->readTid(), inst->seqNum, (*list_it));
 
-        addrList[tid].erase(vect_it);
+        addrList[tid].erase(list_it);
 
         // Erase From Address Map (Used for Debugging)
         addrMap[tid].erase(addrMap[tid].find(mem_addr));
diff -r 26a0b8a1ecb8 -r 9ccf5354e3a4 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh   Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh   Sun Jun 19 21:43:38 2011 -0400
@@ -187,9 +187,9 @@
 
     bool cachePortBlocked;
 
-    std::vector<Addr> addrList[ThePipeline::MaxThreads];
+    std::list<Addr> addrList[ThePipeline::MaxThreads];
 
-    std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
+    m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 
   public:
     int cacheBlkSize;
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