changeset dd3e52966c26 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dd3e52966c26
description:
inorder: redefine DynInst FP result type
Sharing the FP value w/the integer values was giving inconsistent
results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
diffstat:
src/cpu/inorder/cpu.cc | 28 +++++++++++++-
src/cpu/inorder/cpu.hh | 6 ---
src/cpu/inorder/inorder_dyn_inst.cc | 57 ++++++++++++++++------------
src/cpu/inorder/inorder_dyn_inst.hh | 45 ++++++++++++----------
src/cpu/inorder/reg_dep_map.cc | 11 +++--
src/cpu/inorder/resources/execution_unit.cc | 21 ++++++++--
src/cpu/inorder/resources/use_def.cc | 15 ++++---
7 files changed, 116 insertions(+), 67 deletions(-)
diffs (truncated from 504 to 300 lines):
diff -r 76dd3a85e4ae -r dd3e52966c26 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:38 2011 -0400
+++ b/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:38 2011 -0400
@@ -195,6 +195,7 @@
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
+ stCondFails(0),
#if FULL_SYSTEM
system(params->system),
physmem(system->physmem),
@@ -206,6 +207,7 @@
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
+ lastRunningCycle(0),
instsPerSwitch(0)
{
ThreadID active_threads;
@@ -258,6 +260,9 @@
}
for (ThreadID tid = 0; tid < numThreads; ++tid) {
+ pc[tid].set(0);
+ lastCommittedPC[tid].set(0);
+
#if FULL_SYSTEM
// SMT is not supported in FS mode yet.
assert(numThreads == 1);
@@ -1170,12 +1175,18 @@
FloatReg
InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
{
+ DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
+ tid, reg_idx, floatRegs.i[tid][reg_idx],
floatRegs.f[tid][reg_idx]);
+
return floatRegs.f[tid][reg_idx];
}
FloatRegBits
InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
-{;
+{
+ DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
+ tid, reg_idx, floatRegs.i[tid][reg_idx],
floatRegs.f[tid][reg_idx]);
+
return floatRegs.i[tid][reg_idx];
}
@@ -1199,6 +1210,11 @@
InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
{
floatRegs.f[tid][reg_idx] = val;
+ DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
+ "%x, %08f\n",
+ tid, reg_idx,
+ floatRegs.i[tid][reg_idx],
+ floatRegs.f[tid][reg_idx]);
}
@@ -1206,6 +1222,11 @@
InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
{
floatRegs.i[tid][reg_idx] = val;
+ DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
+ "%x, %08f\n",
+ tid, reg_idx,
+ floatRegs.i[tid][reg_idx],
+ floatRegs.f[tid][reg_idx]);
}
uint64_t
@@ -1257,6 +1278,11 @@
MiscReg
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
{
+ DPRINTF(InOrderCPU, "MiscReg: %i\n", misc_reg);
+ DPRINTF(InOrderCPU, "tid: %i\n", tid);
+ DPRINTF(InOrderCPU, "tcBase: %x\n", tcBase(tid));
+ DPRINTF(InOrderCPU, "isa-tid: %x\n", &isa[tid]);
+
return isa[tid].readMiscReg(misc_reg, tcBase(tid));
}
diff -r 76dd3a85e4ae -r dd3e52966c26 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:38 2011 -0400
+++ b/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:38 2011 -0400
@@ -262,17 +262,11 @@
*/
unsigned fetchPortIdx;
- /** Identifies the resource id that identifies a ITB */
- unsigned itbIdx;
-
/** Identifies the resource id that identifies a data
* access unit.
*/
unsigned dataPortIdx;
- /** Identifies the resource id that identifies a DTB */
- unsigned dtbIdx;
-
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];
diff -r 76dd3a85e4ae -r dd3e52966c26 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Sun Jun 19 21:43:38 2011 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Sun Jun 19 21:43:38 2011 -0400
@@ -69,8 +69,6 @@
lqIdx(0), sqIdx(0), instListIt(NULL), onInstList(false)
{
for(int i = 0; i < MaxInstSrcRegs; i++) {
- instSrc[i].integer = 0;
- instSrc[i].dbl = 0;
_readySrcRegIdx[i] = false;
_srcRegIdx[i] = 0;
}
@@ -124,9 +122,6 @@
nextStage = 0;
- for(int i = 0; i < MaxInstDestRegs; i++)
- instResult[i].val.integer = 0;
-
status.reset();
memAddrReady = false;
@@ -355,39 +350,48 @@
void
InOrderDynInst::setIntSrc(int idx, uint64_t val)
{
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] Int being set "
"to %#x.\n", threadNumber, seqNum, idx, val);
- instSrc[idx].integer = val;
+ instSrc[idx].intVal = val;
}
/** Records an fp register being set to a value. */
void
InOrderDynInst::setFloatSrc(int idx, FloatReg val)
{
- instSrc[idx].dbl = val;
+ instSrc[idx].fpVal.f = val;
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FP being set "
+ "to %x, %08f...%08f\n", threadNumber, seqNum, idx,
+ instSrc[idx].fpVal.i, instSrc[idx].fpVal.f, val);
}
/** Records an fp register being set to an integer value. */
void
-InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
+InOrderDynInst::setFloatRegBitsSrc(int idx, FloatRegBits val)
{
- instSrc[idx].integer = val;
+ instSrc[idx].fpVal.i = val;
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPBits being set "
+ "to %x, %08f...%x\n", threadNumber, seqNum, idx,
+ instSrc[idx].fpVal.i, instSrc[idx].fpVal.f, val);
}
/** Reads a integer register. */
IntReg
InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
{
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
- threadNumber, seqNum, idx, instSrc[idx].integer);
- return instSrc[idx].integer;
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] IntVal read as %#x.\n",
+ threadNumber, seqNum, idx, instSrc[idx].intVal);
+ return instSrc[idx].intVal;
}
/** Reads a FP register. */
FloatReg
InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
{
- return instSrc[idx].dbl;
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPVal being read "
+ "as %x, %08f.\n", threadNumber, seqNum, idx,
+ instSrc[idx].fpVal.i, instSrc[idx].fpVal.f);
+ return instSrc[idx].fpVal.f;
}
@@ -395,7 +399,10 @@
FloatRegBits
InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
{
- return instSrc[idx].integer;
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPBits being read "
+ "as %x, %08f.\n", threadNumber, seqNum, idx,
+ instSrc[idx].fpVal.i, instSrc[idx].fpVal.f);
+ return instSrc[idx].fpVal.i;
}
/** Reads a miscellaneous register. */
@@ -414,8 +421,8 @@
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
" read as %#x.\n", threadNumber, seqNum, idx,
- instSrc[idx].integer);
- return instSrc[idx].integer;
+ instSrc[idx].intVal);
+ return instSrc[idx].intVal;
}
@@ -427,7 +434,7 @@
const MiscReg &val)
{
instResult[idx].type = Integer;
- instResult[idx].val.integer = val;
+ instResult[idx].res.intVal = val;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
@@ -457,7 +464,7 @@
InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
instResult[idx].type = Integer;
- instResult[idx].val.integer = val;
+ instResult[idx].res.intVal = val;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
@@ -469,13 +476,13 @@
void
InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
- instResult[idx].val.dbl = val;
+ instResult[idx].res.fpVal.f = val;
instResult[idx].type = Float;
instResult[idx].tick = curTick();
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
- "being set to %#x (result-tick:%i).\n",
- threadNumber, seqNum, idx, val, instResult[idx].tick);
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Result Float Reg. %i "
+ "being set to %#x, %08f (result-tick:%i).\n",
+ threadNumber, seqNum, idx, val, val, instResult[idx].tick);
}
/** Sets a FP register as a integer. */
@@ -484,10 +491,10 @@
FloatRegBits val)
{
instResult[idx].type = Integer;
- instResult[idx].val.integer = val;
+ instResult[idx].res.fpVal.i = val;
instResult[idx].tick = curTick();
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Result Float Reg. Bits %i "
"being set to %#x (result-tick:%i).\n",
threadNumber, seqNum, idx, val, instResult[idx].tick);
}
diff -r 76dd3a85e4ae -r dd3e52966c26 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Sun Jun 19 21:43:38 2011 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Sun Jun 19 21:43:38 2011 -0400
@@ -89,6 +89,8 @@
// Floating point register type.
typedef TheISA::FloatReg FloatReg;
// Floating point register type.
+ typedef TheISA::FloatRegBits FloatRegBits;
+ // Floating point register type.
typedef TheISA::MiscReg MiscReg;
typedef short int PhysRegIndex;
@@ -207,13 +209,6 @@
/** How many source registers are ready. */
unsigned readyRegs;
- /** An instruction src/dest has to be one of these types */
- union InstValue {
- uint64_t integer;
- double dbl;
- };
-
- //@TODO: Naming Convention for Enums?
enum ResultType {
None,
Integer,
@@ -221,19 +216,30 @@
Double
};
+ /** An instruction src/dest has to be one of these types */
+ struct InstValue {
+ IntReg intVal;
+ union {
+ FloatReg f;
+ FloatRegBits i;
+ } fpVal;
+
+ InstValue()
+ {
+ intVal = 0;
+ fpVal.i = 0;
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