changeset 10b13dcd6bb8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=10b13dcd6bb8
description:
inorder: remove stalls on trap squash
diffstat:
src/cpu/inorder/comm.hh | 20 ++++++++++++++--
src/cpu/inorder/inorder_dyn_inst.hh | 3 +-
src/cpu/inorder/pipeline_stage.cc | 33 +++++++++++++++++++++++++++-
src/cpu/inorder/reg_dep_map.cc | 4 +-
src/cpu/inorder/resources/fetch_seq_unit.cc | 15 ++++++++++++-
5 files changed, 66 insertions(+), 9 deletions(-)
diffs (199 lines):
diff -r a2396560f01c -r 10b13dcd6bb8 src/cpu/inorder/comm.hh
--- a/src/cpu/inorder/comm.hh Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/comm.hh Sun Jun 19 21:43:37 2011 -0400
@@ -55,18 +55,32 @@
/** Struct that defines all backwards communication. */
struct TimeStruct {
- struct stageComm {
+ struct StageComm {
bool squash;
InstSeqNum doneSeqNum;
bool uncached;
ThePipeline::DynInstPtr uncachedLoad;
+
+ StageComm()
+ : squash(false), doneSeqNum(0), uncached(false), uncachedLoad(NULL)
+ { }
};
- stageComm stageInfo[ThePipeline::NumStages][ThePipeline::MaxThreads];
-
+ StageComm stageInfo[ThePipeline::NumStages][ThePipeline::MaxThreads];
bool stageBlock[ThePipeline::NumStages][ThePipeline::MaxThreads];
bool stageUnblock[ThePipeline::NumStages][ThePipeline::MaxThreads];
+
+ TimeStruct()
+ {
+ for (int i = 0; i < ThePipeline::NumStages; i++) {
+ for (int j = 0; j < ThePipeline::MaxThreads; j++) {
+ stageBlock[i][j] = false;
+ stageUnblock[i][j] = false;
+ }
+ }
+ }
+
};
#endif //__CPU_INORDER_COMM_HH__
diff -r a2396560f01c -r 10b13dcd6bb8 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Sun Jun 19 21:43:37 2011 -0400
@@ -314,7 +314,8 @@
// BASE INSTRUCTION INFORMATION.
//
////////////////////////////////////////////////////////////
- std::string instName() { return staticInst->getName(); }
+ std::string instName()
+ { return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
void setMachInst(ExtMachInst inst);
diff -r a2396560f01c -r 10b13dcd6bb8 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/pipeline_stage.cc Sun Jun 19 21:43:37 2011 -0400
@@ -226,6 +226,7 @@
}
if (!stalls[tid].resources.empty()) {
+#if TRACING_ON
string stall_src;
for (int i=0; i < stalls[tid].resources.size(); i++) {
@@ -234,6 +235,7 @@
DPRINTF(InOrderStage,"[tid:%i]: Stall fom resources (%s) detected.\n",
tid, stall_src);
+#endif
ret_val = true;
}
@@ -294,8 +296,11 @@
stageStatus[tid] = Blocked;
- if (prevStageValid)
+ if (prevStageValid) {
+ DPRINTF(InOrderStage, "[tid:%d]: Stage %i setting block signal.\n",
+ tid, stageNum);
toPrevStages->stageBlock[stageNum][tid] = true;
+ }
return true;
}
@@ -323,6 +328,7 @@
bool
PipelineStage::unblock(ThreadID tid)
{
+ // @todo: Shouldnt this be if any available slots are open???
// Stage is done unblocking only if the skid buffer is empty.
if (skidBuffer[tid].empty()) {
DPRINTF(InOrderStage, "[tid:%u]: Done unblocking.\n", tid);
@@ -623,6 +629,13 @@
for (int stage_idx = stageNum+1; stage_idx <= lastStallingStage[tid];
stage_idx++) {
+ DPRINTF(InOrderStage, "[tid:%i] Reading stall signals from Stage "
+ "%i. Block:%i Unblock:%i.\n",
+ tid,
+ stage_idx,
+ fromNextStages->stageBlock[stage_idx][tid],
+ fromNextStages->stageUnblock[stage_idx][tid]);
+
// Check for Stage Blocking Signal
if (fromNextStages->stageBlock[stage_idx][tid]) {
DPRINTF(InOrderStage, "[tid:%i] Stall from stage %i set.\n", tid,
@@ -637,6 +650,20 @@
stalls[tid].stage[stage_idx] = false;
}
}
+
+ for (int stage_idx = 0; stage_idx < NumStages;
+ stage_idx++) {
+
+ DPRINTF(InOrderStage, "[tid:%i] Stall signals from Stage "
+ "%i. Block:%i Unblock:%i...NBlock:%i NUnblock:%i\n",
+ tid,
+ stage_idx,
+ fromNextStages->stageBlock[stage_idx][tid],
+ fromNextStages->stageUnblock[stage_idx][tid],
+ toPrevStages->stageBlock[stage_idx][tid],
+ toPrevStages->stageUnblock[stage_idx][tid]);
+ }
+
}
@@ -866,7 +893,9 @@
inst = insts_to_stage.front();
DPRINTF(InOrderStage, "[tid:%u]: Processing instruction [sn:%lli] "
- "with PC %s\n", tid, inst->seqNum, inst->pcState());
+ "%s with PC %s\n", tid, inst->seqNum,
+ inst->instName(),
+ inst->pcState());
if (inst->isSquashed()) {
DPRINTF(InOrderStage, "[tid:%u]: Instruction %i with PC %s is "
diff -r a2396560f01c -r 10b13dcd6bb8 src/cpu/inorder/reg_dep_map.cc
--- a/src/cpu/inorder/reg_dep_map.cc Sun Jun 19 21:43:37 2011 -0400
+++ b/src/cpu/inorder/reg_dep_map.cc Sun Jun 19 21:43:37 2011 -0400
@@ -105,7 +105,7 @@
inst->flattenDestReg(i, flat_idx);
if (flat_idx == TheISA::ZeroReg) {
- DPRINTF(IntRegs, "[sn:%i]: Ignoring Insert-Dependency tracking for
"
+ DPRINTF(RegDepMap, "[sn:%i]: Ignoring Insert-Dependency tracking
for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
continue;
@@ -145,7 +145,7 @@
RegIndex flat_idx = inst->flattenedDestRegIdx(i);
if (flat_idx == TheISA::ZeroReg) {
- DPRINTF(IntRegs, "[sn:%i]: Ignoring Remove-Dependency tracking
for "
+ DPRINTF(RegDepMap, "[sn:%i]: Ignoring Remove-Dependency
tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
continue;
diff -r a2396560f01c -r 10b13dcd6bb8 src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:37
2011 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:37
2011 -0400
@@ -116,6 +116,9 @@
// If it's a return, then we must wait for resolved
address.
// The Predictor will mark a return a false as "not taken"
// if there is no RAS entry
+ DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting block signal "
+ "for stage %i.\n",
+ tid, stage_num);
cpu->pipelineStage[stage_num]->
toPrevStages->stageBlock[stage_num][tid] = true;
pcValid[tid] = false;
@@ -215,8 +218,16 @@
// Unblock Any Stages Waiting for this information to be updated
...
if (!pcValid[tid]) {
+ DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting unblock signal "
+ "for stage %i.\n",
+ tid, pcBlockStage[tid]);
+
+ // Need to use "fromNextStages" instead of "toPrevStages"
+ // because the timebuffer will have already have advanced
+ // in the tick function and this squash function will happen
after
+ // the tick
cpu->pipelineStage[pcBlockStage[tid]]->
- toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
+ fromNextStages->stageUnblock[pcBlockStage[tid]][tid] =
true;
}
pcValid[tid] = true;
@@ -291,6 +302,8 @@
"%s.\n", tid, pc[tid]);
DPRINTF(InOrderFetchSeq, "[tid:%i]: Trap updating to PC: "
"%s.\n", tid, pc[tid]);
+
+ cpu->removePipelineStalls(tid);
}
void
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